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Design Exploration of Dynamic Multi-Level Ternary Content-Addressable Memory Using Nanoelectromechanical Relays.

T. Li, H. Zhong, S. George, V. Narayanan, L. Shi, H. Yang, and X. Li. ISVLSI, page 1-6. IEEE, (2023)

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P Narayanan

Hermine Narayanan

Vidya Narayanan

Narayanan Radhakrishnan

Narayanan Sundaram

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Power Analysis Attack Resistance Engineering by Dynamic Voltage and Frequency Scaling.S. Yang, P. Gupta, M. Wolf, D. Serpanos, V. Narayanan, and Y. Xie. ACM Trans. Embed. Comput. Syst., 11 (3): 62:1-62:16 (2012)An Accuracy Tunable Non-Boolean Co-Processor Using Coupled Nano-Oscillators.N. Gala, S. Krithivasan, W. Tsai, X. Li, V. Narayanan, and V. Kamakoti. ACM J. Emerg. Technol. Comput. Syst., 14 (1): 1:1-1:28 (2018)Nonvolatile Processor Architecture Exploration for Energy-Harvesting Applications.K. Ma, X. Li, S. Li, Y. Liu, J. Sampson, Y. Xie, and V. Narayanan. IEEE Micro, 35 (5): 32-40 (2015)Process-Variation-Aware Adaptive Cache Architecture and Management.M. Mutyam, F. Wang, K. Ramakrishnan, V. Narayanan, M. Kandemir, Y. Xie, and M. Irwin. IEEE Trans. Computers, 58 (7): 865-877 (2009)A reconfigurable platform for the design and verification of domain-specific accelerators.S. Park, Y. Cho, K. Irick, and V. Narayanan. ASP-DAC, page 108-113. IEEE, (2012)Managing Leakage Energy in Cache Hierarchies.L. Li, I. Kadayif, Y. Tsai, N. Vijaykrishnan, M. Kandemir, M. Irwin, and A. Sivasubramaniam. J. Instruction-Level Parallelism, (2003)On the Effects of Process Variation in Network-on-Chip Architectures.C. Nicopoulos, S. Srinivasan, A. Yanamandra, D. Park, V. Narayanan, C. Das, and M. Irwin. IEEE Trans. Dependable Secur. Comput., 7 (3): 240-254 (2010)On the Detection of Clones in Sensor Networks Using Random Key Predistribution.R. Brooks, P. Govindaraju, M. Pirretti, N. Vijaykrishnan, and M. Kandemir. IEEE Trans. Syst. Man Cybern. Part C, 37 (6): 1246-1258 (2007)Harnessing ferroelectrics for non-volatile memories and logic.S. Gupta, D. Wang, S. George, A. Aziz, X. Li, S. Datta, and V. Narayanan. ISQED, page 29-34. IEEE, (2017)X-VS: Crossbar-Based Processing-in-Memory Architecture for Video Summarization.N. Challapalle, M. Chandran, S. Rampalli, and V. Narayanan. ISVLSI, page 592-597. IEEE, (2020)

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Disambiguation of "Narayanan, Vijaykrishnan"

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Design Exploration of Dynamic Multi-Level Ternary Content-Addressable Memory Using Nanoelectromechanical Relays.

Please choose a person to relate this publication to

P Narayanan

Hermine Narayanan

Vidya Narayanan

Narayanan Radhakrishnan

Narayanan Sundaram

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Narayanan, Vijaykrishnan"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Design Exploration of Dynamic Multi-Level Ternary Content-Addressable Memory Using Nanoelectromechanical Relays.

Please choose a person to relate this publication to

P Narayanan

Hermine Narayanan

Vidya Narayanan

Narayanan Radhakrishnan

Narayanan Sundaram

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Design Exploration of Dynamic Multi-Level Ternary Content-Addressable Memory Using Nanoelectromechanical Relays.