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Staged Reads: Mitigating the impact of DRAM writes on DRAM reads., , , , и . HPCA, стр. 41-52. IEEE Computer Society, (2012)CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory., , , , , и . DATE, стр. 33-38. IEEE, (2012)Design trade-offs for high density cross-point resistive memory., , , , и . ISLPED, стр. 209-214. ACM, (2012)Understanding the trade-offs in multi-level cell ReRAM memory design., , , , и . DAC, стр. 108:1-108:6. ACM, (2013)Interconnect design considerations for large NUCA caches., и . ISCA, стр. 369-380. ACM, (2007)Rethinking DRAM design and organization for energy-constrained multi-cores., , , , , и . ISCA, стр. 175-186. ACM, (2010)Improving memristor memory with sneak current sharing., , , и . ICCD, стр. 549-556. IEEE Computer Society, (2015)LOT-ECC: Localized and tiered reliability mechanisms for commodity memory systems., , , , и . ISCA, стр. 285-296. IEEE Computer Society, (2012)Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0., , и . MICRO, стр. 3-14. IEEE Computer Society, (2007)The role of optics in future high radix switch design., , , , , , и . ISCA, стр. 437-448. ACM, (2011)