( en | de | ru )

 

Disambiguation of "der Plas, Geert Van"

Author of the publication

copydeleteadd this publication to your clipboard
Digital ground bounce reduction by supply current shaping and clock frequency Modulation.

, , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (1): 65-76 (2005)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Kai Marc Geertsema

Stefaan Van der Vekens

Christian van der Steeg

Christian van der Linde

Adrianus van der Hoeven

 

Other publications of authors with the same name

A 2.2mW 5b 1.75GS/s Folding Flash ADC in 90nm Digital CMOS., , , , and . ISSCC, page 252-253. IEEE, (2008)Systematic design of a 14-bit 150-MS/s CMOS current-steering D/A converter., , , , , and . DAC, page 452-457. ACM, (2000)A 12 bit 200 MHz low glitch CMOS D/A converter., , , , , , , , and . CICC, page 249-252. IEEE, (1998)A gradient-error and edge-effect tolerant switching scheme for a high-accuracy DAC., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 51-I (1): 191-195 (2004)Design issues in heterogeneous 3D/2.5D integration., , , , , and . ASP-DAC, page 403-410. IEEE, (2013)Impact of technology scaling on substrate noise generation mechanisms mixed signal ICs., , , , , and . CICC, page 501-504. IEEE, (2004)Thermal experimental and modeling analysis of high power 3D packages., , , , , and . ICICDT, page 1-4. IEEE, (2015)Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance., , , and . DATE, page 270-275. IEEE Computer Society, (2005)In-tier diagnosis of power domains in 3D TSV ICs., , , , , , , , , and 1 other author(s). 3DIC, page 1-6. IEEE, (2011)Active-lite interposer for 2.5 & 3D integration., , , , , , , , , and 5 other author(s). VLSIC, page 222-. IEEE, (2015)