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Disambiguation of "Waidyasooriya, Hasitha Muthumala"

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Implementation of a custom hardware-accelerator for short-read mapping using Burrows-Wheeler alignment.

, , and . EMBC, page 651-654. IEEE, (2013)

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Karunasiri Muthumala

 

Other publications of authors with the same name

Benchmarks for FPGA-Targeted High-Level-Synthesis., , and . CANDAR, page 232-238. IEEE, (2019)Implementation of an FPGA-Oriented Complex Number Computation Library Using Intel OneAPI DPC++., , and . MWSCAS, page 1-4. IEEE, (2022)Hardware-oriented succinct-data-structure based on block-size-constrained compression., , and . SoCPaR, page 136-140. IEEE, (2015)A Memory-Bandwidth-Efficient Word2vec Accelerator Using OpenCL for FPGA., , , , , , and . CANDAR Workshops, page 103-108. IEEE, (2019)OpenCL-Based FPGA Accelerator for 3D FDTD with Periodic and Absorbing Boundary Conditions., , , and . Int. J. Reconfigurable Comput., (2017)Data-Transfer-Aware Design of an FPGA-Based Heterogeneous Multicore Platform with Custom Accelerators., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 98-A (12): 2658-2669 (2015)Architecture of an FPGA-Based Heterogeneous System for Code-Search Problems., , , and . SCFA, volume 10776 of Lecture Notes in Computer Science, page 146-155. Springer, (2018)Data-Transfer-Bottleneck-Less Architecture for FPGA-Based Quantum Annealing Simulation., , and . CANDAR, page 164-170. IEEE, (2019)Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation., , , , , and . IEICE Trans. Electron., 95-C (12): 1872-1882 (2012)FPGA implementation of heterogeneous multicore platform with SIMD/MIMD custom accelerators., , , and . ISCAS, page 1339-1342. IEEE, (2012)