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Benchmarks for FPGA-Targeted High-Level-Synthesis., , and . CANDAR, page 232-238. IEEE, (2019)Hardware-oriented succinct-data-structure based on block-size-constrained compression., , and . SoCPaR, page 136-140. IEEE, (2015)Implementation of an FPGA-Oriented Complex Number Computation Library Using Intel OneAPI DPC++., , and . MWSCAS, page 1-4. IEEE, (2022)Architecture of an FPGA-Based Heterogeneous System for Code-Search Problems., , , and . SCFA, volume 10776 of Lecture Notes in Computer Science, page 146-155. Springer, (2018)Data-Transfer-Bottleneck-Less Architecture for FPGA-Based Quantum Annealing Simulation., , and . CANDAR, page 164-170. IEEE, (2019)OpenCL-Based FPGA Accelerator for 3D FDTD with Periodic and Absorbing Boundary Conditions., , , and . Int. J. Reconfigurable Comput., (2017)Data-Transfer-Aware Design of an FPGA-Based Heterogeneous Multicore Platform with Custom Accelerators., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 98-A (12): 2658-2669 (2015)A Memory-Bandwidth-Efficient Word2vec Accelerator Using OpenCL for FPGA., , , , , , and . CANDAR Workshops, page 103-108. IEEE, (2019)Mapping for a Heterogeneous Multi-Core Media Processor Considering the Data Transfer Time., , , and . ERSA, page 281-284. CSREA Press, (2010)Architecture of an FPGA-Oriented Heterogeneous Multi-core Processor with SIMD-Accelerator Cores., , and . ERSA, page 179-186. CSREA Press, (2010)