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Comparing Static and Dynamic Code Scheduling for Multiple-Instruction-Issue Processors.

, , , and . MICRO, page 25-33. ACM/IEEE, (1991)

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Toward Application-Aware Security and Reliability., , , , , , and . IEEE Secur. Priv., 5 (1): 57-62 (2007)The superblock: An effective technique for VLIW and superscalar compilation., , , , , , , , , and 2 other author(s). J. Supercomput., 7 (1-2): 229-248 (1993)Incremental Compiler Transformations for Multiple Instruction Retry., , , and . Softw. Pract. Exp., 24 (12): 1179-1198 (1994)Advanced MRI reconstruction toolbox with accelerating on GPU., , , , , , , , and . Parallel Processing for Imaging Applications, volume 7872 of SPIE Proceedings, page 78720Q. SPIE, (2011)Adaptive Cache Bypass and Insertion for Many-core Accelerators., , , , , , and . MES, page 1-8. ACM, (2014)Heterogeneous Computing Meets Near-Memory Acceleration and High-Level Synthesis in the Post-Moore Era., , , and . IEEE Micro, 37 (4): 10-18 (2017)An efficient GPU implementation and scaling for higher-order 3D stencils., , , and . Inf. Sci., (2022)Bottom-Up and Top-Down Context-Sensitive Summary-Based Pointer Analysis., , and . SAS, volume 3148 of Lecture Notes in Computer Science, page 165-180. Springer, (2004)Critical issues regarding HPS, a high performance microarchitecture., , , and . MICRO, page 109-116. ACM/IEEE, (1985)HPS, a new microarchitecture: rationale and introduction., , and . MICRO, page 103-108. ACM/IEEE, (1985)