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Disambiguation of "Huang, Ru"

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Design Considerations of Multi-Level 1S1R Cell for In-Memory Computing.

, , , , and . ICTA, page 144-145. IEEE, (2023)

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Ru-Jin Huang

Ru Zhang

Ru Xie

Tomasz Ru

Ru Hao

 

Other publications of authors with the same name

Heterogeneous integration of nano enabling devices for 3D ICs., , , , , , , , , and 7 other author(s). ISLPED, page 249-254. IEEE, (2013)The design of energy-saving filtering mechanism for sensor networks., and . ICMLC, page 79-85. IEEE, (2010)20.2 A 57nW Software-Defined Always-On Wake-Up Chip for IoT Devices with Asynchronous Pipelined Event-Driven Architecture and Time-Shielding Level-Crossing ADC., , , , , , and . ISSCC, page 314-316. IEEE, (2020)Compact Modeling of Phase Change Memory with Parameter Extractions., , , , , , , , and . ESSDERC, page 308-311. IEEE, (2022)First Foundry Platform Demonstration of Hybrid Tunnel FET and MOSFET Circuits Based on a Novel Laminated Well Isolation Technology., , , , , , , , , and 8 other author(s). ESSDERC, page 13-16. IEEE, (2023)Session 16 Overview: Computation in Memory Memory Subcommittee., , and . ISSCC, page 244-245. IEEE, (2021)A 7.9fJ/Conversion-Step and 37.12aFrms Pipelined-SAR Capacitance-to-Digital Converter with kT/C Noise Cancellation and Incomplete-Settling-Based Correlated Level Shifting., , , , , , , , , and . ISSCC, page 346-347. IEEE, (2023)30.5 A Variation-Tolerant In-eDRAM Continuous-Time Ising Machine Featuring 15-Level Coefficients and Leaked Negative-Feedback Annealing., , , , , , , , and . ISSCC, page 490-492. IEEE, (2024)SWIFT: Small-World-based Structural Pruning to Accelerate DNN Inference on FPGA., , , , and . FPGA, page 148. ACM, (2021)9.4 A 182.3dB FoMs 50MS/s Pipelined-SAR ADC using Cascode Capacitively Degenerated Dynamic Amplifier and MSB Pre-Conversion Technique., , , , , , , , , and 1 other author(s). ISSCC, page 174-176. IEEE, (2024)