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Disambiguation of "Mochizuki, Akira"

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Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure.

, , , , , , , , , , and . VLSIC, page 172-. IEEE, (2015)

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Akira Hayashima

Akira Hori

Akira Satake

Akira Hayashima

Akira Yasui

 

Other publications of authors with the same name

Complementary 5T-4MTJ nonvolatile TCAM cell circuit with phase-selective parallel writing scheme., , , , , , , and . IEICE Electron. Express, 11 (10): 20140297 (2014)Design of an energy-efficient 2T-2MTJ nonvolatile TCAM based on a parallel-serial-combined search scheme., , , , and . IEICE Electron. Express, 11 (3): 20131006 (2014)Multiple-Valued Duplex Asynchronous Data Transfer Scheme for Interleaving in LDPC Decoders., , and . ISMVL, page 138-143. IEEE Computer Society, (2005)Design of a Microprocessor Datapath Using Four-Valued Differential-Pair Circuits., , , and . ISMVL, page 14. IEEE Computer Society, (2006)High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs., , , , , and . IEICE Trans. Inf. Syst., 97-D (6): 1546-1556 (2014)Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply Dual-Rail Source-Coupled Logic., , and . ISMVL, page 64-71. IEEE Computer Society, (1995)Design of a Quaternary Single-Ended Current-Mode Circuit for an Energy-Efficient Inter-chip Asynchronous Communication Link., , and . ISMVL, page 67-72. IEEE Computer Society, (2014)Intra-Chip Address-Presetting Data-Transfer Scheme Using Four-Valued Encoding., , and . ISMVL, page 192-197. IEEE Computer Society, (2004)Highly reliable single-ended current-mode circuit for an inter-chip asynchronous communication link., , , and . APCCAS, page 683-686. IEEE, (2014)Multiple-Valued Dynamic Source-Coupled Logic., , and . ISMVL, page 207-212. IEEE Computer Society, (2003)