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Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure.

D. Suzuki, M. Natsui, A. Mochizuki, S. Miura, H. Honjo, H. Sato, S. Fukami, S. Ikeda, T. Endoh, H. Ohno, and T. Hanyu. VLSIC, page 172-. IEEE, (2015)

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Tetsuo Morino

Tetsuo Kishimoto

Other publications of authors with the same name

0.18- μm CMOS 10-Gb/s multiplexer/demultiplexer ICs using current mode logic with tolerance to threshold voltage fluctuation.A. Tanabe, M. Umetani, I. Fujiwara, T. Ogura, K. Kataoka, M. Okihara, H. Sakuraba, T. Endoh, and F. Masuoka. IEEE J. Solid State Circuits, 36 (6): 988-996 (2001)Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing.T. Hanyu, T. Endoh, D. Suzuki, H. Koike, Y. Ma, N. Onizawa, M. Natsui, S. Ikeda, and H. Ohno. Proc. IEEE, 104 (10): 1844-1863 (2016)A compact and low power logic design for multi-pillar vertical MOSFETs.K. Sakui, and T. Endoh. ISCAS, page 309-312. IEEE, (2010)Accurate error bit mode analysis of STT-MRAM chip with a novel current measurement module implemented to gigabit class memory test system.R. Tamura, I. Mori, N. Watanabe, H. Koike, and T. Endoh. NVMTS, page 1-5. IEEE, (2018)Neuromorphic processor-oriented hybrid Q-format multiplication with adaptive quantization for tiny YOLO3.T. Li, Y. Ma, and T. Endoh. Neural Comput. Appl., 35 (15): 11013-11041 (May 2023)Nonvolatile logic and memory devices based on spintronics.T. Endoh. ISCAS, page 13-16. IEEE, (2015)A novel memory test system with an electromagnet for STT-MRAM testing.R. Tamura, N. Watanabe, H. Koike, H. Sato, S. Ikeda, T. Endoh, and S. Sato. NVMTS, page 1-4. IEEE, (2019)A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing.R. Nebashi, N. Sakimura, H. Honjo, A. Morioka, Y. Tsuji, K. Ishihara, K. Tokutome, S. Miura, S. Fukami, K. Kinoshita and 5 other author(s). ISCAS, page 1588-1591. IEEE, (2014)Stochastic behavior-considered VLSI CAD environment for MTJ/MOS-hybrid microprocessor design.M. Natsui, A. Tamakoshi, A. Mochizuki, H. Koike, H. Ohno, T. Endoh, and T. Hanyu. ISCAS, page 1878-1881. IEEE, (2016)Study on Impurity Distribution Dependence of Electron-Dynamics in Vertical MOSFET.M. Muraguchi, and T. Endoh. IEICE Trans. Electron., 94-C (5): 737-742 (2011)

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Disambiguation of "Endoh, Tetsuo"

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Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure.

Please choose a person to relate this publication to

Tetsuo Morino

Tetsuo Kishimoto

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Endoh, Tetsuo"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure.

Please choose a person to relate this publication to

Tetsuo Morino

Tetsuo Kishimoto

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
BibTeX
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APA
Chicago
DIN 1505
Harvard
MSOffice XML

Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure.