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Yield-Driven Near-Threshold SRAM Design., , , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (11): 1590-1598 (2010)Modeling and Analysis of Parametric Yield under Power and Performance Constraints., , , and . IEEE Des. Test Comput., 22 (4): 376-385 (2005)A Variation-Tolerant Sub-200 mV 6-T Subthreshold SRAM., , , and . IEEE J. Solid State Circuits, 43 (10): 2338-2348 (2008)Leakage Current: Moore's Law Meets Static Power., , , , , , , , and . Computer, 36 (12): 68-75 (2003)Postroute gate sizing for crosstalk noise reduction., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (12): 1670-1677 (2004)Design and Evaluation of Confidence-Driven Error-Resilient Systems., , , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (8): 1727-1737 (2014)Gate oxide leakage current analysis and reduction for VLSI circuits., , and . IEEE Trans. Very Large Scale Integr. Syst., 12 (2): 155-166 (2004)Ultra-low power circuit techniques for a new class of sub-mm3 sensor nodes., , , , and . CICC, page 1-8. IEEE, (2010)A sub-pW timer using gate leakage for ultra low-power sub-Hz monitoring systems., , and . CICC, page 397-400. IEEE, (2007)A 0.5V 2.2pW 2-transistor voltage reference., , , and . CICC, page 577-580. IEEE, (2009)