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On-Line Techniques for Error Detection and Correction in Processor Registers with Cross-Parity Check., , , и . J. Electron. Test., 19 (5): 501-510 (2003)Perspectives of Combining on-line and off-line Test Technology for Dependable Systems on a Chip., , и . IOLTS, стр. 183-. IEEE Computer Society, (2003)A Hierarchical Self Test Scheme for SoCs., , и . IOLTS, стр. 37-44. IEEE Computer Society, (2004)On-line Detection and Compensation of Transient Errors in Processor Pipeline-Structures., , и . IOLTW, стр. 178. IEEE Computer Society, (2002)On-Line Error Detection and Correction in Storage Elements with Cross-Parity Check., , , и . IOLTW, стр. 69-73. IEEE Computer Society, (2002)A Configurable Modular Test Processor and Scan Controller Architecture., , , , и . IOLTS, стр. 277-284. IEEE Computer Society, (2007)A new method for on-line state machine observation for embedded microprocessors., , и . HLDVT, стр. 34-39. IEEE Computer Society, (2000)Logic Self Repair., , и . ARCS Workshops, том P-81 из LNI, стр. 36-44. GI, (2006)A Test Processor Concept for Systems-on-a-Chip., , и . ICCD, стр. 210-. IEEE Computer Society, (2002)Embedded Scan Test with Diagnostic Features for Self-Testing SoCs., , , , , и . IOLTS, стр. 181-182. IEEE Computer Society, (2006)