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Test Instruction Set (TIS) for High Level Self-Testing of CPU Cores.

S. Shamshiri, H. Esmaeilzadeh, and Z. Navabi. Asian Test Symposium, page 158-163. IEEE Computer Society, (2004)

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Kambiz Navabi

Foroogh Navabi-Kermani

Other publications of authors with the same name

SCOAP-based Directed Random Test Generation for Combinational Circuits.S. Ghasemy, M. Rajabalipanah, S. Sarmadi, and Z. Navabi. EWDTS, page 1-5. IEEE, (2019)An Accelerator-based Architecture Utilizing an Efficient Memory Link for Modern Computational Requirements.S. Yousefzadeh, K. Basharkhah, N. Nosrati, R. Sadeghi, J. Raik, M. Jenihhin, and Z. Navabi. EWDTS, page 1-6. IEEE, (2019)DCim++: a C++ library for object oriented hardware design and distributed simulation.H. Esmaeilzadeh, A. Moghimi, E. Ebrahimi, C. Lucas, Z. Navabi, and A. Fakhraie. ISCAS, IEEE, (2006)A near-threshold 7T SRAM cell with high write and read margins and low write time for sub-20 nm FinFET technologies.M. Ansari, H. Afzali-Kusha, B. Ebrahimi, Z. Navabi, A. Afzali-Kusha, and M. Pedram. Integr., (2015)An efficient BIST method for testing of embedded SRAMs.M. Tehranipour, Z. Navabi, and S. Fakhraie. ISCAS (5), page 73-76. IEEE, (2001)Programmable Routing Tables for Degradable Torus-Based Networks on Chips.A. Shahabi, N. Honarmand, and Z. Navabi. ISCAS, page 1065-1068. IEEE, (2007)A Low Power BIST Architecture for FPGA Look-Up Table Testing.E. Atoofian, and Z. Navabi. VLSI-SOC, page 394-397. Technische Universität Darmstadt, Insitute of Microelectronic Systems, (2003)Modeling Timing Behavior of Logic Circuits Using Piecewise Linear Models.Z. Navabi, A. Hashemi, M. Eghtesad, and M. Vai. CHDL, volume A-32 of IFIP Transactions, page 569-586. North-Holland, (1993)Using Verilog VPI for Mixed Level Serial Fault Simulation in a Test Generation Environment.P. Riahi, Z. Navabi, and F. Lombardi. Embedded Systems and Applications, page 139-143. CSREA Press, (2003)Near-Optimal Node Selection Procedure for Aging Monitor Placement.S. Kohan, A. Vafaei, and Z. Navabi. IOLTS, page 6-11. IEEE, (2018)

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Disambiguation of "Navabi, Zainalabedin"

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Test Instruction Set (TIS) for High Level Self-Testing of CPU Cores.

Please choose a person to relate this publication to

Kambiz Navabi

Foroogh Navabi-Kermani

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Navabi, Zainalabedin"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Test Instruction Set (TIS) for High Level Self-Testing of CPU Cores.

Please choose a person to relate this publication to

Kambiz Navabi

Foroogh Navabi-Kermani

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Test Instruction Set (TIS) for High Level Self-Testing of CPU Cores.