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CoreGenesis: erasing core boundaries for robust and configurable performance.

, , , , and . PACT, page 571-572. ACM, (2010)

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Bridging the computation gap between programmable processors and hardwired accelerators., , , and . HPCA, page 313-322. IEEE Computer Society, (2009)DVFS in loop accelerators using BLADES., , , , and . DAC, page 894-897. ACM, (2008)CoreGenesis: erasing core boundaries for robust and configurable performance., , , , and . PACT, page 571-572. ACM, (2010)A Deep Dive Into Understanding The Random Walk-Based Temporal Graph Learning., , , , , , , , and . IISWC, page 87-100. IEEE, (2021)Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache., , , , , , and . CGO, page 179-190. IEEE Computer Society, (2005)A 1GHz hardware loop-accelerator with razor-based dynamic adaptation for energy-efficient operation., , , and . CICC, page 1-4. IEEE, (2013)Power-efficient medical image processing using PUMA., , and . SASP, page 29-34. IEEE Computer Society, (2009)PEPSC: A Power-Efficient Processor for Scientific Computing., , , and . PACT, page 101-110. IEEE Computer Society, (2011)A 1 GHz Hardware Loop-Accelerator With Razor-Based Dynamic Adaptation for Energy-Efficient Operation., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (8): 2290-2298 (2014)Power-Efficient Accelerators for High-Performance Applications.. University of Michigan, USA, (2011)