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pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture.

K. Koo, S. Ok, Y. Kang, S. Kim, C. Song, H. Lee, H. Kim, Y. Kim, J. Lee, S. Oak, Y. Lee, J. Lee, J. Lee, H. Lee, J. Jang, J. Jung, B. Choi, Y. Kim, Y. Hur, Y. Kim, B. Chung, and Y. Kim. ISSCC, page 40-41. IEEE, (2012)

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Ky ng Kim

Die Artikelstruktur in passiven zweisprachigen Wörterbüchern Deutsch-Koreanisch: Konzeption zur Erstellung eines zweisprachigen Lernerwörterbuchs Deutsch-KoreanischK. Kim. Uni Heidelberg, (2008)

Kison Kim

Wonchan Kim

Bongcheol Kim

Kim Gerber

Other publications of authors with the same name

A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture.K. Koo, S. Ok, Y. Kang, S. Kim, C. Song, H. Lee, H. Kim, Y. Kim, J. Lee, S. Oak and 12 other author(s). ISSCC, page 40-41. IEEE, (2012)System Optimization of Data Analytics Platforms using Compute Express Link (CXL) Memory.S. Ryu, S. Kim, J. Jun, D. Moon, K. Lee, J. Choi, S. Kim, H. Kim, L. Kim, W. Choi and 4 other author(s). BigComp, page 9-12. IEEE, (2023)Design and Implementation of Quantum Key Distribution Network Control and Management.T. Choi, S. Yoon, T. Kim, and H. Kim. ICTC, page 724-727. IEEE, (2021)Efficient transmit antenna selection for correlated MIMO channels.H. Kim, H. Kim, N. Kim, H. Park, S. Seo, and J. Choi. WCNC, page 27-31. IEEE, (2009)Co-modeling, Experimental Verification, and Analysis of Chip-Package Hierarchical Power Distribution Network.H. Park, H. Kim, J. Pak, C. Yoon, K. Koo, and J. Kim. IEICE Trans. Electron., 91-C (4): 595-606 (2008)Energy/carbon management network for IT equipments.S. Chang, H. Kim, B. Chung, and H. Jung. APNOMS, page 1-5. IEEE, (2012)A 1.3-4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line.H. Park, J. Sim, Y. Choi, J. Choi, Y. Kwon, S. Park, G. Park, J. Chung, K. Kim, H. Jung and 3 other author(s). IEEE J. Solid State Circuits, 56 (6): 1886-1896 (2021)Chip-package hybrid clock distribution network and DLL for low jitter clock delivery.D. Chung, C. Ryu, H. Kim, C. Lee, J. Kim, K. Bae, J. Yu, H. Yoo, and J. Kim. IEEE J. Solid State Circuits, 41 (1): 274-286 (2006)Crosstalk-included eye-diagram estimation for high-speed silicon, organic, and glass interposer channels on 2.5D/3D IC.S. Choi, H. Kim, D. Jung, J. Kim, J. Lim, H. Lee, K. Cho, J. Kim, H. Kim, Y. Kim and 1 other author(s). 3DIC, page TS8.25.1-TS8.25.5. IEEE, (2015)A 4.35Gb/s/pin LPDDR4 I/O interface with multi-VOH level, equalization scheme, and duty-training circuit for mobile applications.H. Jung, J. Yang, J. Lee, H. Ko, H. Lee, T. Song, J. Shim, S. Lee, K. Song, D. Kim and 2 other author(s). VLSIC, page 184-. IEEE, (2015)

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Disambiguation of "Kim, Hyungsoo"

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A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture.

Please choose a person to relate this publication to

Ky ng Kim

Kison Kim

Wonchan Kim

Bongcheol Kim

Kim Gerber

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Kim, Hyungsoo"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture.

Please choose a person to relate this publication to

Ky ng Kim

Kison Kim

Wonchan Kim

Bongcheol Kim

Kim Gerber

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture.