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Disambiguation of "Mak, Pui-In"

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Fully Symmetrical Obfuscated Interconnection and Weak-PUF-Assisted Challenge Obfuscation Strong PUFs Against Machine-Learning Modeling Attacks.

, , , , and . IEEE Trans. Inf. Forensics Secur., (2024)

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Ellen Mak

Beatrice Puiu

Rebecca Mak

Kwok Mak

Ale PuÌ

 

Other publications of authors with the same name

An I/Q-multiplexed and OTA-shared CMOS pipelined ADC with an A-DQS S/H front-end for two-step-channel-select low-IF receiver., , , , , , , and . ISCAS (1), page 1068-1071. IEEE, (2004)Session 21 overview: Smart SoCs for innovative applications., , and . ISSCC, page 350-351. IEEE, (2017)A 0.02-to-6GHz SDR balun-LNA using a triple-stage inverter-based amplifier., , and . ISCAS, page 472-475. IEEE, (2012)A 2-µW 45-nV/√Hz Readout Front End With Multiple-Chopping Active-High-Pass Ripple Reduction Loop and Pseudofeedback DC Servo Loop., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 63-II (4): 351-355 (2016)Object Recognition Test in Peripheral Vision: A Study on the Influence of Object Color, Pattern and Shape., , , , , , , , , and 1 other author(s). Brain Informatics, volume 7670 of Lecture Notes in Computer Science, page 18-26. Springer, (2012)A SAW-Less Tunable RF Front End for FDD and IBFD Combining an Electrical-Balance Duplexer and a Switched-LC N-Path LNA., , , , and . IEEE J. Solid State Circuits, 53 (5): 1431-1442 (2018)A 0.0071-mm2 10.8pspp-Jitter 4 to 10-Gb/s 5-Tap Current-Mode Transmitter Using a Hybrid Delay Line for Sub-1-UI Fractional De-Emphasis., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (10): 3991-4004 (2019)A 3.6-mW 6-GHz current-reuse VCO-buffer with improved load drivability in 65-nm CMOS., , and . Int. J. Circuit Theory Appl., 43 (1): 133-138 (2015)A regulation-free sub-0.5V 16/24MHz crystal oscillator for energy-harvesting BLE radios with 14.2nJ startup energy and 31.8pW steady-state power., , , and . ISSCC, page 52-54. IEEE, (2018)A 0.0285-mm2 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS., , , and . IEEE J. Solid State Circuits, 57 (2): 546-561 (2022)