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Disambiguation of "Fan, Deliang"

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Reducing SRAM Reading Power With Column Data Segment and Weights Correlation Enhancement for CNN Processing.

, , , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (11): 2237-2250 (2021)

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Deliang Wang

Deliang Chen

Hua Fan

Fan Zhang

Fan Dai

 

Other publications of authors with the same name

GraphS: A Graph Processing Accelerator Leveraging SOT-MRAM., , , and . DATE, page 378-383. IEEE, (2019)Design and Synthesis of Ultra Low Energy Spin-Memristor Threshold Logic., , and . CoRR, (2014)Spin Neurons: A Possible Path to Energy-Efficient Neuromorphic Computers., , and . CoRR, (2013)Hierarchical Temporal Memory Based on Spin-Neurons and Resistive Memory for Energy-Efficient Brain-Inspired Computing., , , and . IEEE Trans. Neural Networks Learn. Syst., 27 (9): 1907-1919 (2016)Artificial Neuron using Ag/2D-MoS2/Au Threshold Switching Memristor., , , , , , , , , and . DRC, page 193-194. IEEE, (2019)Voltage-Based Concatenatable Full Adder Using Spin Hall Effect Switching., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (12): 2134-2138 (2017)Spin-Transfer Torque Devices for Logic and Memory: Prospects and Perspectives., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (1): 1-22 (2016)Leveraging spintronic devices for ultra-low power in-memory computing: Logic and neural network., , and . MWSCAS, page 1109-1112. IEEE, (2017)RADAR: Run-time Adversarial Weight Attack Detection and Accuracy Recovery., , , , and . DATE, page 790-795. IEEE, (2021)Deep-Dup: An Adversarial Weight Duplication Attack Framework to Crush Deep Neural Network in Multi-Tenant FPGA., , , and . USENIX Security Symposium, page 1919-1936. USENIX Association, (2021)