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Disambiguation of "De, Vivek"

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Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors.

, , , , , , , and . DAC, page 486-491. ACM, (2002)

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Nagarajavel Vivekananthan

Vivek Venkataramani

Vivek Ramamurthy

Vivek Bose

Vivek Shetty

 

Other publications of authors with the same name

8.1 Improved power-side-channel-attack resistance of an AES-128 core via a security-aware integrated buck voltage regulator., , , , , and . ISSCC, page 142-143. IEEE, (2017)F1: Designing secure systems: Manufacturing, circuits and architectures., , , , , , and . ISSCC, page 492-494. IEEE, (2016)A solar-powered 280mV-to-1.2V wide-operating-range IA-32 processor., , and . ICICDT, page 1-4. IEEE, (2014)20.1 A digitally controlled fully integrated voltage regulator with on-die solenoid inductor with planar magnetic core in 14nm tri-gate CMOS., , , , , , , , , and . ISSCC, page 336-337. IEEE, (2017)On-Chip High-Resolution Timing Characterization Circuits for Memory IPs., , , , , , and . ESSCIRC, page 377-380. IEEE, (2022)A 10Mbit, 15GBytes/sec bandwidth 1T DRAM chip with planar MOS storage capacitor in an unmodified 150nm logic process for high-density on-chip memory applications., , , , , , and . ESSCIRC, page 355-358. IEEE, (2005)Resiliency for many-core system on a chip., , , , , , and . ASP-DAC, page 388-389. IEEE, (2014)A Modular Hybrid LDO with Fast Load-Transient Response and Programmable PSRR in 14nm CMOS Featuring Dynamic Clamp Tuning and Time-Constant Compensation., , , , , , , and . ISSCC, page 234-236. IEEE, (2019)Conductance modulation techniques in switched-capacitor DC-DC converter for maximum-efficiency tracking and ripple mitigation in 22nm Tri-gate CMOS., , , , , and . CICC, page 1-4. IEEE, (2014)A 2.3nJ/frame Voice Activity Detector based audio front-end for context-aware System-on-Chip applications in 32nm CMOS., , , , , and . CICC, page 1-4. IEEE, (2012)