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Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors.

T. Karnik, Y. Ye, J. Tschanz, L. Wei, S. Burns, V. Govindarajulu, V. De, and S. Borkar. DAC, page 486-491. ACM, (2002)

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Calum Burns

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The ISPD-2012 discrete cell sizing contest and benchmark suite.M. Ozdal, C. Amin, A. Ayupov, S. Burns, G. Wilke, and C. Zhuo. ISPD, page 161-164. ACM, (2012)Comparative Analysis of Conventional and Statistical Design Techniques.S. Burns, M. Ketkar, N. Menezes, K. Bowman, J. Tschanz, and V. De. DAC, page 238-243. IEEE, (2007)Reusing GEMM Hardware for Efficient Execution of Depthwise Separable Convolution on ASIC-Based DNN Accelerators.S. Manasi, S. Banerjee, A. Davare, A. Sorokin, S. Burns, D. Kirkpatrick, and S. Sapatnekar. ASP-DAC, page 475-482. ACM, (2023)A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement.T. Dhar, R. S, J. Poojary, S. Yaldiz, S. Burns, R. Harjani, and S. Sapatnekar. DATE, page 148-153. IEEE, (2022)Energy Efficient Architecture for Graph Analytics Accelerators.M. Ozdal, S. Yesil, T. Kim, A. Ayupov, J. Greth, S. Burns, and Ö. Özturk. ISCA, page 166-177. IEEE Computer Society, (2016)Learning from Experience: Applying ML to Analog Circuit Design.K. Kunal, T. Dhar, Y. Li, M. Madhusudan, J. Poojary, A. Sharma, W. Xu, S. Burns, R. Harjani, J. Hu and 2 other author(s). ISPD, page 55. ACM, (2020)Practical applications of an efficient time separation of events algorithm.H. Hulgaard, S. Burns, T. Amon, and G. Borriello. ICCAD, page 146-151. IEEE Computer Society / ACM, (1993)An FPGA for Implementing Asynchronous Circuits.S. Hauck, S. Burns, G. Borriello, and C. Ebeling. IEEE Des. Test Comput., 11 (3): 60-69 (1994)The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk).T. Dhar, K. Kunal, Y. Li, Y. Lin, M. Madhusudan, J. Poojary, A. Sharma, S. Burns, R. Harjani, J. Hu and 3 other author(s). ICCAD, page 54:1-54:2. IEEE, (2020)Synthesis of asynchronous control circuits with automatically generated relative timing assumptions.J. Cortadella, M. Kishinevsky, S. Burns, and K. Stevens. ICCAD, page 324-331. IEEE Computer Society, (1999)

BibSonomy

Disambiguation of "Burns, Steven M."

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Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors.

Please choose a person to relate this publication to

Calum Burns

Barbara Burns

Nicola Burns

Glen Burns

John Burns

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Burns, Steven M."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors.

Please choose a person to relate this publication to

Calum Burns

Barbara Burns

Nicola Burns

Glen Burns

John Burns

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors.