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Disambiguation of "Schäfer, Benjamin Carrión"

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Micro-architecture Tuning for Dynamic Frequency Scaling in Coarse-Grain Runtime Reconfigurable Arrays with Adaptive Clock Domain Support.

, , and . ISVLSI, page 212-217. IEEE, (2021)

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Benjamin Schäfer

Christoph Benjamin Schäfer

Ruperto Antonio Ugas Carrión

Monika Borst-Carrión Eguiguren

Víctor Manuel Pérez Abreu Carrión

 

Other publications of authors with the same name

Approximating Behavioral HW Accelerators through Selective Partial Extractions onto Synthesizable Predictive Models., and . ICCAD, page 1-8. ACM, (2019)Low Power Design of Runtime Reconfigurable FPGAs through Contexts Approximations., and . ICCD, page 524-531. IEEE, (2019)Precision tunable RTL macro-modelling cycle-accurate power estimation., and . IET Comput. Digit. Tech., 5 (2): 95-103 (2011)Efficient Functional Locking of Behavioral IPs., and . MWSCAS, page 639-642. IEEE, (2020)Autonomous temperature control technique in VLSI circuits through logic replication., and . IET Comput. Digit. Tech., 3 (1): 62-71 (2009)CERTIFY: AutomatiC MEasuRing The QualIty oF High-Level SYnthesis., , and . ISCAS, page 1-5. IEEE, (2023)Accelerating FPGA Prototyping through Predictive Model-Based HLS Design Space Exploration., , and . DAC, page 97. ACM, (2019)Functional Obfuscation of Hardware Accelerators through Selective Partial Design Extraction onto an Embedded FPGA., , , , , , , and . ACM Great Lakes Symposium on VLSI, page 171-176. ACM, (2019)PEPA: Performance Enhancement of Embedded Processors through HW Accelerator Resource Sharing., and . ACM Great Lakes Symposium on VLSI, page 23-28. ACM, (2023)Investigation and Optimization of Pin Multiplexing in High-Level Synthesis., , and . ACM Great Lakes Symposium on VLSI, page 427-430. ACM, (2018)