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A 100 MHz-Reference, 10.3-to-11.1 GHz Quadrature PLL with 33.7-fsrms Jitter and -83.9 dBc Reference Spur Level using a -130.8 dBc/Hz Phase Noise at 1MHz offset Folded Series-Resonance VCO in 65nm CMOS., , , , , , и . CICC, стр. 1-2. IEEE, (2023)An Enhanced Class-F Dual-Core VCO With Common-Mode-Noise Self-Cancellation and Isolation Technique., , , , , , , и . IEEE J. Solid State Circuits, 59 (8): 2441-2454 (августа 2024)An 11.4-to-16.4GHz FMCW Digital PLL with Cycle-slipping Compensation and Back-tracking DPD Achieving 0.034% RMS Frequency Error under 3.4-GHz Chirp Bandwidth and 960-MHz/μs Chirp Slope., , , , , , , , и . VLSI Technology and Circuits, стр. 1-2. IEEE, (2023)A 4.8-GHz Time-Interleaved Multi-Reference PLL with 16.1-fs Jitter., , , , , и . ESSCIRC, стр. 261-264. IEEE, (2023)A 4.7GHz Synchronized-Multi-Reference PLL with In-Band Phase Noise Lower than Reference Phase Noise +20logNdiv., , , , , , , и . ESSCIRC, стр. 233-236. IEEE, (2022)A Multireference PLL: Theory and Implementation., , , , , , и . IEEE J. Solid State Circuits, 59 (7): 1981-1994 (июля 2024)IEEE ASSCC 2023/ Session 10/ Paper 10.5., , , , , и . A-SSCC, стр. 1-3. IEEE, (2023)An 11.5-to-14.3GHz 192.8dBc/Hz FoM at 1MHz Offset Dual-Core Enhanced Class-F VCO with Common-Mode-Noise Self-Cancellation and Isolation Technique., , , , , , и . ISSCC, стр. 146-147. IEEE, (2023)An 11.1-to-14.9GHz Digital-Integral Hybrid-Proportional Fractional-N PLL with an LC DTC Achieving 0.52μs Locking Time and 41.3f5 Jitter., , , и . CICC, стр. 1-2. IEEE, (2024)