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An 11.4-to-16.4GHz FMCW Digital PLL with Cycle-slipping Compensation and Back-tracking DPD Achieving 0.034% RMS Frequency Error under 3.4-GHz Chirp Bandwidth and 960-MHz/μs Chirp Slope.

A. Yan, W. Deng, H. Jia, S. Sun, C. Tang, B. Zhu, Y. Fu, H. Liu, and B. Chi. VLSI Technology and Circuits, page 1-2. IEEE, (2023)

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Liu Liu

Keetsin Liu

Ching Liu

Other publications of authors with the same name

A 100 MHz-Reference, 10.3-to-11.1 GHz Quadrature PLL with 33.7-fsrms Jitter and -83.9 dBc Reference Spur Level using a -130.8 dBc/Hz Phase Noise at 1MHz offset Folded Series-Resonance VCO in 65nm CMOS.S. Zhang, W. Deng, H. Jia, H. Liu, S. Sun, P. Guan, and B. Chi. CICC, page 1-2. IEEE, (2023)An 11.4-to-16.4GHz FMCW Digital PLL with Cycle-slipping Compensation and Back-tracking DPD Achieving 0.034% RMS Frequency Error under 3.4-GHz Chirp Bandwidth and 960-MHz/μs Chirp Slope.A. Yan, W. Deng, H. Jia, S. Sun, C. Tang, B. Zhu, Y. Fu, H. Liu, and B. Chi. VLSI Technology and Circuits, page 1-2. IEEE, (2023)An Enhanced Class-F Dual-Core VCO With Common-Mode-Noise Self-Cancellation and Isolation Technique.Q. Wu, W. Deng, Y. Sun, H. Jia, H. Liu, S. Zhang, Z. Wang, and B. Chi. IEEE J. Solid State Circuits, 59 (8): 2441-2454 (August 2024)A 4.8-GHz Time-Interleaved Multi-Reference PLL with 16.1-fs Jitter.H. Liu, W. Deng, H. Jia, S. Zhang, S. Sun, and B. Chi. ESSCIRC, page 261-264. IEEE, (2023)A 4.7GHz Synchronized-Multi-Reference PLL with In-Band Phase Noise Lower than Reference Phase Noise +20logNdiv.H. Liu, W. Deng, H. Jia, S. Sun, Q. Wu, J. Tang, Z. Wang, and B. Chi. ESSCIRC, page 233-236. IEEE, (2022)A Multireference PLL: Theory and Implementation.H. Liu, W. Deng, H. Jia, S. Zhang, S. Sun, Z. Wang, and B. Chi. IEEE J. Solid State Circuits, 59 (7): 1981-1994 (July 2024)An 11.5-to-14.3GHz 192.8dBc/Hz FoM at 1MHz Offset Dual-Core Enhanced Class-F VCO with Common-Mode-Noise Self-Cancellation and Isolation Technique.Q. Wu, W. Deng, H. Jia, H. Liu, S. Zhang, Z. Wang, and B. Chi. ISSCC, page 146-147. IEEE, (2023)IEEE ASSCC 2023/ Session 10/ Paper 10.5.R. Ma, H. Jia, H. Liu, W. Deng, Z. Wang, and B. Chi. A-SSCC, page 1-3. IEEE, (2023)An 11.1-to-14.9GHz Digital-Integral Hybrid-Proportional Fractional-N PLL with an LC DTC Achieving 0.52μs Locking Time and 41.3f5 Jitter.H. Liu, W. Deng, H. Jia, and B. Chi. CICC, page 1-2. IEEE, (2024)

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Disambiguation of "Liu, Hongzhuo"

Please choose a person to relate this publication to

Liu Liu

Liu Liu

Liu Liu

Keetsin Liu

Ching Liu

Other publications of authors with the same name

Disambiguation