From post

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

 

Другие публикации лиц с тем же именем

International Solid-State Circuits Conference 2019 aims at "envisioning the future"., и . Sci. China Inf. Sci., 62 (6): 67401:1-67401:2 (2019)A Compact E-Band Load-Modulation Balanced Power Amplifier Using Coupled Transmission-Line Output Network Achieving 22.1-dBm Psat and 34.9%/12.2% Efficiency at Psat/6-dB PBO., , , , и . A-SSCC, стр. 1-3. IEEE, (2023)An 8.2-to-21.5 GHz Dual-Core Quad-Mode Orthogonal-Coupled VCO with Concurrently Dual-Output using Parallel 8-Shaped Resonator., , , , , , и . CICC, стр. 1-2. IEEE, (2021)An Enhanced Class-F Dual-Core VCO With Common-Mode-Noise Self-Cancellation and Isolation Technique., , , , , , , и . IEEE J. Solid State Circuits, 59 (8): 2441-2454 (августа 2024)An 11.4-to-16.4GHz FMCW Digital PLL with Cycle-slipping Compensation and Back-tracking DPD Achieving 0.034% RMS Frequency Error under 3.4-GHz Chirp Bandwidth and 960-MHz/μs Chirp Slope., , , , , , , , и . VLSI Technology and Circuits, стр. 1-2. IEEE, (2023)A 122-168GHz Radar/Communication Fusion-Mode Transceiver with 30GHz Chirp Bandwidth, 13dBm Psat, and 8.3dBm OP1dB in 28nm CMOS., , , , , , , , , и 3 other автор(ы). VLSI Circuits, стр. 1-2. IEEE, (2021)A Fully Integrated QPSK/16-QAM D-Band CMOS Transceiver With Mixed-Signal Baseband Circuitry Realizing Digital Interfaces., , , , , , , , , и 3 other автор(ы). IEEE J. Solid State Circuits, 59 (10): 3123-3141 (октября 2024)A 4.8-GHz Time-Interleaved Multi-Reference PLL with 16.1-fs Jitter., , , , , и . ESSCIRC, стр. 261-264. IEEE, (2023)A 44-52 GHz Reflection-type Phase Shifter with 1.4° Phase Resolution in 28nm CMOS Process., , , , и . ICTA, стр. 15-16. IEEE, (2020)Optimization methods for high inductance-density inductors for high speed integrated circuits., , , , и . ICTA, стр. 243-244. IEEE, (2021)