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Disambiguation of "Somasekhar, Dinesh"

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2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process.

, , , , , , , , , , and . ISSCC, page 274-275. IEEE, (2008)

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Dinesh Lathia

Dinesh Adhikary

Dinesh Thilakarathna

Dinesh Subramaniam

Dinesh Kumar Takyar

 

Other publications of authors with the same name

System-Level Power Analysis of a Multicore Multipower Domain Processor With ON-Chip Voltage Regulators., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (12): 3468-3476 (2016)LVDCSL: low voltage differential current switch logic, a robust low power DCSL family., and . ISLPED, page 18-23. ACM, (1997)Leakage control with efficient use of transistor stacks in single threshold CMOS., , , and . IEEE Trans. Very Large Scale Integr. Syst., 10 (1): 1-5 (2002)Evaluation of differential vs. single-ended sensing and asymmetric cells in 90 nm logic technology for on-chip caches., , , and . ISCAS, IEEE, (2006)A 6-GHz 16-kB L1 cache in a 100-nm dual-VT technology using a bitline leakage reduction (BLR) technique., , , , and . IEEE J. Solid State Circuits, 38 (5): 839-842 (2003)2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process., , , , , , , , , and 1 other author(s). ISSCC, page 274-275. IEEE, (2008)IDD Waveforms Analysis for Testing of Domino and Low Voltage Static CMOS Circuits., , and . Great Lakes Symposium on VLSI, page 243-248. IEEE Computer Society, (1998)Leakage Control with Efficient Use of Transistor Stacks in Single Threshold CMOS., , and . DAC, page 442-445. ACM Press, (1999)5-GHz 32-bit integer execution core in 130-nm dual-VT CMOS., , , , , , , , , and 12 other author(s). IEEE J. Solid State Circuits, 37 (11): 1421-1432 (2002)A 10Mbit, 15GBytes/sec bandwidth 1T DRAM chip with planar MOS storage capacitor in an unmodified 150nm logic process for high-density on-chip memory applications., , , , , , and . ESSCIRC, page 355-358. IEEE, (2005)