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A 4.2GHz 0.3mm2 256kb Dual-Vcc SRAM Building Block in 65nm CMOS., , , , , , , , , and 3 other author(s). ISSCC, page 2572-2581. IEEE, (2006)A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS., , , , , , , , , and 11 other author(s). ISSCC, page 66-68. IEEE, (2012)An IA-32 processor with a wide voltage operating range in 32nm CMOS., , , , , , , , , and 9 other author(s). Hot Chips Symposium, page 1-37. IEEE, (2012)The 48-core SCC Processor: the Programmer's View., , , , , , , , , and 1 other author(s). SC, page 1-11. IEEE, (2010)2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process., , , , , , , , , and 1 other author(s). ISSCC, page 274-275. IEEE, (2008)An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS., , , , , , , , , and 4 other author(s). ISSCC, page 98-589. IEEE, (2007)A 2 Tb/s 6 , ˟, 4 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOS., , , , , , , , and . IEEE J. Solid State Circuits, 46 (4): 757-766 (2011)Using the Altera UP-1 Board for Prototyping and VGA Video Display Generation., and . MSE, page 16-17. IEEE Computer Society, (1999)