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Optimized ASIP architecture for compressed BWT-indexed search in bioinformatics applications.

, , and . HPCS, page 527-534. IEEE, (2014)

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Optimized ASIP architecture for compressed BWT-indexed search in bioinformatics applications., , and . HPCS, page 527-534. IEEE, (2014)Optimization of area under a delay constraint in digital filter synthesis using SAT-based integer linear programming., , , and . DAC, page 669-674. ACM, (2006)Optimization of gate-level area in high throughput Multiple Constant Multiplications., , , and . ECCTD, page 588-591. IEEE, (2011)ASSUMEs: Heuristic Algorithms for Optimization of Area and Delay in Digital Filter Synthesis., , , and . ICECS, page 748-751. IEEE, (2006)Efficient shift-adds design of digit-serial multiple constant multiplications., , , , and . ACM Great Lakes Symposium on VLSI, page 61-66. ACM, (2011)An exact algorithm for the maximal sharing of partial terms in multiple constant multiplications., , and . ICCAD, page 13-16. IEEE Computer Society, (2005)Exploration of tradeoffs in the design of integer cosine transforms for image compression., , , and . ECCTD, page 1-4. IEEE, (2013)Minimum number of operations under a general number representation for digital filter synthesis., , , and . ECCTD, page 252-255. IEEE, (2007)Assignment and Reordering of Incompletely Specified Pattern Sequences Targetting Minimum Power Dissipation., , , , and . VLSI Design, page 37-41. IEEE Computer Society, (1999)Optimization of design complexity in time-multiplexed constant multiplications., , and . DATE, page 1-4. European Design and Automation Association, (2014)