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A composable worst case latency analysis for multi-rank DRAM devices under open row policy., , и . Real Time Syst., 52 (6): 761-807 (2016)HopliteBuf: FPGA NoCs with Provably Stall-Free FIFOs., , , и . FPGA, стр. 222-231. ACM, (2019)A Requests Bundling DRAM Controller for Mixed-Criticality Systems., и . RTAS, стр. 247-258. IEEE Computer Society, (2017)Memory Servers for Multicore Systems., и . RTAS, стр. 97-108. IEEE Computer Society, (2016)ASIIST: Application Specific I/O Integration Support Tool for Real-Time Bus Architecture Designs., , , и . ICECCS, стр. 11-22. IEEE Computer Society, (2009)A design-space exploration for allocating security tasks in multicore real-time systems., , , и . DATE, стр. 225-230. IEEE, (2018)Toward the Predictable Integration of Real-Time COTS Based Systems., и . RTSS, стр. 73-82. IEEE Computer Society, (2007)A Slot-Based Real-Time Scheduling Algorithm for Concurrent Transactions in NoC., , и . RTCSA (1), стр. 329-338. IEEE Computer Society, (2011)A Tight Holistic Memory Latency Bound Through Coordinated Management of Memory Resources., , , , и . ECRTS, том 262 из LIPIcs, стр. 17:1-17:25. Schloss Dagstuhl - Leibniz-Zentrum für Informatik, (2023)Duetto: Latency Guarantees at Minimal Performance Cost., , и . DATE, стр. 1136-1141. IEEE, (2021)