( en | de | ru )

 

Disambiguation of "Papanikolaou, Antonis"

Author of the publication

copydeleteadd this publication to your clipboard
A tool flow for predicting system level timing failures due to interconnect reliability degradation.

, , , , , and . ACM Great Lakes Symposium on VLSI, page 291-296. ACM, (2008)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Georgios Papanikolaou

Paschalis Papanikolaou

Apostolos Papanikolaou

Amalia Papanikolaou

Antonis Tsiongas

 

Other publications of authors with the same name

Fast Design Space Exploration Environment Applied on NoC's for 3D-Stacked MPSoC's., , , , , , and . ARCS Workshops, page 319-324. VDE Verlag, (2010)Classification Framework for Analysis and Modeling of Physically Induced Reliability Violations., , , , , , , and . ACM Comput. Surv., 47 (3): 38:1-38:33 (2015)Topology exploration for energy efficient intra-tile communication., , and . ASP-DAC, page 178-183. IEEE Computer Society, (2007)Power, performance and area prediction of 3D ICs during early stage design exploration in 45nm., , , , and . ICECS, page 715-718. IEEE, (2011)Physical design implementation of segmented buses to reduce communication energy., , , and . ASP-DAC, page 42-47. IEEE, (2006)Interconnect exploration for future wire dominated technologies., , , , , , , and . SLIP, page 105-106. ACM, (2002)3-D Technology Assessment: Path-Finding the Technology/Design Sweet-Spot., , , , , , , , and . Proc. IEEE, 97 (1): 96-107 (2009)Reliability issues in deep deep sub-micron technologies: time-dependent variability and its impact on embedded system design., , , , , , , , and . VLSI-SoC, page 342-347. IEEE, (2006)Accelerating All-to-All Protein Structures Comparison with TMalign Using a NoC Many-Cores Processor Architecture., , and . IPDPS Workshops, page 510-519. IEEE, (2013)A global bus power optimization methodology for physical design of memory dominated systems by coupling bus segmentation and activity driven block placement., , , and . ASP-DAC, page 759-761. IEEE Computer Society, (2004)