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A tool flow for predicting system level timing failures due to interconnect reliability degradation.

J. Guo, A. Papanikolaou, M. Stucchi, K. Croes, Z. Tokei, and F. Catthoor. ACM Great Lakes Symposium on VLSI, page 291-296. ACM, (2008)

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Zsolt Zrinyi

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A tool flow for predicting system level timing failures due to interconnect reliability degradation.J. Guo, A. Papanikolaou, M. Stucchi, K. Croes, Z. Tokei, and F. Catthoor. ACM Great Lakes Symposium on VLSI, page 291-296. ACM, (2008)Layout dependency induced deviation from Poisson area scaling in BEOL dielectric reliability.Y. Li, Z. Tökei, P. Roussel, G. Groeseneken, and K. Maex. Microelectron. Reliab., 45 (9-11): 1299-1304 (2005)First demonstration of Two Metal Level Semi-damascene Interconnects with Fully Self-aligned Vias at 18MP.G. Murdoch, M. O'Toole, G. Marti, A. Pokhrel, D. Tsvetanova, S. Decoster, S. Kundu, Y. Oniki, A. Thiam, Q. Le and 5 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2022)Electromigration limits of copper nano-interconnects.H. Zahedmanesh, O. Pedreira, Z. Tokei, and K. Croes. IRPS, page 1-6. IEEE, (2021)Global Is the New Local: FPGA Architecture at 5nm and Beyond.S. Nikolic, F. Catthoor, Z. Tokei, and P. Ienne. FPGA, page 34-44. ACM, (2021)Low-Frequency Noise Measurements to Characterize Cu-Electromigration Down to 44nm Metal Pitch.S. Beyne, O. Pedreira, I. Wolf, Z. Tökei, and K. Croes. IRPS, page 1-6. IEEE, (2019)Stress mitigation of 3D-stacking/packaging induced stresses.K. Croes, V. Cherman, M. Lofrano, H. Zahedmanesh, L. Kljucar, M. Gonzalez, I. Wolf, Z. Tökei, and E. Beyne. IRPS, page 4. IEEE, (2018)Metal reliability mechanisms in Ruthenium interconnects.O. Pedreira, M. Stucchi, A. Gupta, V. Vega-Gonzalez, M. van der Veen, S. Lariviere, C. Wilson, Z. Tökei, and K. Croes. IRPS, page 1-7. IEEE, (2020)Reliability of a DME Ru Semidamascene scheme with 16 nm wide Airgaps.A. Lesniewska, O. Pedreira, M. Lofrano, G. Murdoch, M. van der Veen, A. Dangol, N. Horiguchi, Z. Tökei, and K. Croes. IRPS, page 1-6. IEEE, (2021)Logic Scaling Options for the Next 10 Years: From FinFet to CFET, from Dual Damascene to Semi Damascene.Z. Tokei. FPGA, page 49. ACM, (2022)

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A tool flow for predicting system level timing failures due to interconnect reliability degradation.

Please choose a person to relate this publication to

Zsolt Zrinyi

Zsolt Szücs

Zsolt Szabó

Zsolt Szentiványi

Zsolt Szabó

Other publications of authors with the same name

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BibSonomy

Disambiguation of "Tokei, Zsolt"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A tool flow for predicting system level timing failures due to interconnect reliability degradation.

Please choose a person to relate this publication to

Zsolt Zrinyi

Zsolt Szücs

Zsolt Szabó

Zsolt Szentiványi

Zsolt Szabó

Other publications of authors with the same name

Disambiguation

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URL
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Chicago
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A tool flow for predicting system level timing failures due to interconnect reliability degradation.