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Metal reliability mechanisms in Ruthenium interconnects.

, , , , , , , , и . IRPS, стр. 1-7. IEEE, (2020)

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Michèle Mattusch

Michele Susca

Michèle Schenker

Michèle Knodt

Michele Fossi

 

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Statistically Aware SRAM Memory Array Design., , , и . ISQED, стр. 25-30. IEEE Computer Society, (2006)3D Stacked IC demonstrator using Hybrid Collective Die-to-Wafer bonding with copper Through Silicon Vias (TSV)., , , , , , , , , и 3 other автор(ы). 3DIC, стр. 1-5. IEEE, (2009)Design issues and considerations for low-cost 3D TSV IC technology., , , , , , , , , и 24 other автор(ы). ISSCC, стр. 148-149. IEEE, (2010)Backside Power Delivery with relaxed overlay for backside patterning using extreme wafer thinning and Molybdenum-filled slit nano Through Silicon Vias., , , , , , , , , и 10 other автор(ы). VLSI Technology and Circuits, стр. 1-2. IEEE, (2024)Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack - Challenges and solutions., , , , , , , , , и 8 other автор(ы). CICC, стр. 1-4. IEEE, (2010)Global interconnect trade-off for technology over memory modules to application level: case study., , , , , , , и . SLIP, стр. 125-132. ACM, (2003)Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 node., , , , , , , , , и 4 other автор(ы). VLSI Technology and Circuits, стр. 1-2. IEEE, (2023)Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails., , , , , , , , , и 34 other автор(ы). VLSI Technology and Circuits, стр. 284-285. IEEE, (2022)Design Issues and Considerations for Low-Cost 3-D TSV IC Technology., , , , , , , , , и 27 other автор(ы). IEEE J. Solid State Circuits, 46 (1): 293-307 (2011)A tool flow for predicting system level timing failures due to interconnect reliability degradation., , , , , и . ACM Great Lakes Symposium on VLSI, стр. 291-296. ACM, (2008)