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A scalable MPEG-4 video codec architecture for IMT-2000 multimedia applications., , , , , , , , , и 7 other автор(ы). ISCAS, стр. 188-191. IEEE, (2000)A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemes., , , , , , , , , и 23 other автор(ы). ISSCC, стр. 464-465. IEEE, (2009)An experimental 2-bit/cell storage DRAM for macrocell or memory-on-logic application., , , , , , , и . IEEE J. Solid State Circuits, 24 (2): 388-393 (апреля 1989)Trends and challenges of large scale embedded memories.. CICC, стр. 449-456. IEEE, (2004)A new CR-delay circuit technology for high-density and high-speed DRAMs., , , и . IEEE J. Solid State Circuits, 24 (4): 905-910 (августа 1989)Variable supply-voltage scheme with 95%-efficiency DC-DC converter for MPEG-4 codec., , , , и . ISLPED, стр. 54-59. ACM, (1999)A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme., , , , , , , , , и 8 other автор(ы). IEEE J. Solid State Circuits, 33 (11): 1772-1780 (1998)Keynote address: Challenges of digital consumer and mobile SoC's: more Moore possible?. DATE, стр. 1. EDA Consortium, San Jose, CA, USA, (2007)Deep sub-100 nm Design Challenges.. ISQED, стр. 13-14. IEEE Computer Society, (2006)A Single-Chip Low-Power Mpeg-4 Audiovisual Lsi Using Embedded Dram Technology., , , и . ICME, IEEE Computer Society, (2001)