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The Camino Compiler infrastructure., , , and . SIGARCH Comput. Archit. News, 33 (5): 3-8 (2005)The impact of cache inclusion policies on cache management techniques., and . MEMSYS, page 428-438. ACM, (2019)Combining Edge Vector and Event Counter for Time-Dependent Power Behavior Characterization., , and . Trans. High Perform. Embed. Archit. Compil., (2009)Fast Path-Based Neural Branch Prediction.. MICRO, page 243-252. IEEE Computer Society, (2003)Insertion and promotion for tree-based PseudoLRU last-level caches.. MICRO, page 284-296. ACM, (2013)Whisper: Profile-Guided Branch Misprediction Elimination for Data Center Applications., , , , , , and . MICRO, page 19-34. IEEE, (2022)Rebasing Microarchitectural Research with Industry Traces., , , and . IISWC, page 100-114. IEEE, (2023)Efficient Program Power Behavior Characterization., , and . HiPEAC, volume 4367 of Lecture Notes in Computer Science, page 183-197. Springer, (2007)Kill the Program Counter: Reconstructing Program Behavior in the Processor Cache Hierarchy., , , , , and . ASPLOS, page 737-749. ACM, (2017)Exploiting Page Table Locality for Agile TLB Prefetching., , , , , , and . ISCA, page 85-98. IEEE, (2021)