( en | de | ru )

 

Disambiguation of "Arimoto, Kazutami"

Author of the publication

copydeleteadd this publication to your clipboard
An 80Gb/s dependable communication SoC with PCI express I/F and 8 CPUs.

, , , , , , , , , , , , , and . ISSCC, page 266-268. IEEE, (2011)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

No persons found for author name Arimoto, Kazutami
add a person with the name Arimoto, Kazutami
 

Other publications of authors with the same name

A Scalable Massively Parallel Processor for Real-Time Image Processing., , , , , , , , , and 9 other author(s). IEEE J. Solid State Circuits, 46 (10): 2363-2373 (2011)400-MHz random column operating SDRAM techniques with self-skew compensation., , , , , , and . IEEE J. Solid State Circuits, 33 (5): 770-778 (1998)A soft-error-immune maintenance-free TCAM architecture with associated embedded DRAM., , , and . CICC, page 451-454. IEEE, (2005)Test Pattern Considerations for Fault Tolerant High Density DRAM., , , , , and . ITC, page 451-455. IEEE Computer Society, (1985)An 80Gb/s dependable communication SoC with PCI express I/F and 8 CPUs., , , , , , , , , and 4 other author(s). ISSCC, page 266-268. IEEE, (2011)Verifying Game Logic in Unreal Engine 5 Blueprint Visual Scripting System Using Model Checking., , , , and . ASE, page 213:1-213:8. ACM, (2022)28-m W Fully Embedded AI Techniques with On-site Learning for Low-Power Handy Tactile Sensing System., , , , , , , and . VLSI-DAT, page 1-4. IEEE, (2022)Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor., , , , and . ISMVL, page 43. IEEE Computer Society, (2007)Dependable SRAM with enhanced read-/write-margins by fine-grained assist bias control for low-voltage operation., , , , , , and . SoCC, page 519-524. IEEE, (2010)An 80 Gbps dependable multicore communication SoC with PCI express I/F and intelligent interrupt controller., , , , , , , , , and 1 other author(s). COOL Chips, page 1-3. IEEE Computer Society, (2011)