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400-MHz random column operating SDRAM techniques with self-skew compensation.

, , , , , , и . IEEE J. Solid State Circuits, 33 (5): 770-778 (1998)

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Hideyuki Sakamoto

 

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A mixed-mode voltage down converter with impedance adjustment circuitry for low-voltage high-frequency memories., , , , , , , , и . IEEE J. Solid State Circuits, 31 (4): 575-585 (1996)A low power and high speed data transfer scheme with asynchronous compressed pulse width modulation for AS-Memory., , и . IEEE J. Solid State Circuits, 31 (4): 523-530 (1996)A precharged-capacitor-assisted sensing (PCAS) scheme with novel level controllers for low-power DRAMs., , , , , и . IEEE J. Solid State Circuits, 35 (8): 1179-1185 (2000)400-MHz random column operating SDRAM techniques with self-skew compensation., , , , , , и . IEEE J. Solid State Circuits, 33 (5): 770-778 (1998)Redundancy Test for 1 Mbit DRAM Using Multi-Bit-Test Mode., , , , , и . ITC, стр. 826-829. IEEE Computer Society, (1986)Design methodology of embedded DRAM with virtual-socket architecture., , , , , , , и . IEEE J. Solid State Circuits, 36 (1): 46-54 (2001)A Low Power Embedded DRAM Macro for Battery-Operated LSIs., , , , , , , , , и 2 other автор(ы). IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 86-A (12): 2991-3000 (2003)