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Disambiguation of "Arimoto, Kazutami"

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Test Pattern Considerations for Fault Tolerant High Density DRAM.

, , , , , and . ITC, page 451-455. IEEE Computer Society, (1985)

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A soft-error-immune maintenance-free TCAM architecture with associated embedded DRAM., , , and . CICC, page 451-454. IEEE, (2005)Test Pattern Considerations for Fault Tolerant High Density DRAM., , , , , and . ITC, page 451-455. IEEE Computer Society, (1985)A Scalable Massively Parallel Processor for Real-Time Image Processing., , , , , , , , , and 9 other author(s). IEEE J. Solid State Circuits, 46 (10): 2363-2373 (2011)400-MHz random column operating SDRAM techniques with self-skew compensation., , , , , , and . IEEE J. Solid State Circuits, 33 (5): 770-778 (1998)Verifying Game Logic in Unreal Engine 5 Blueprint Visual Scripting System Using Model Checking., , , , and . ASE, page 213:1-213:8. ACM, (2022)28-m W Fully Embedded AI Techniques with On-site Learning for Low-Power Handy Tactile Sensing System., , , , , , , and . VLSI-DAT, page 1-4. IEEE, (2022)An 80Gb/s dependable communication SoC with PCI express I/F and 8 CPUs., , , , , , , , , and 4 other author(s). ISSCC, page 266-268. IEEE, (2011)Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor., , , , and . ISMVL, page 43. IEEE Computer Society, (2007)Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor., , , , , , , , and . IEICE Trans. Inf. Syst., 90-D (8): 1312-1315 (2007)Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer., , , , , , , , and . IEICE Trans. Inf. Syst., 90-D (1): 334-345 (2007)