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Disambiguation of "Sathe, Visvesh S."

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Model Predictive Control of an Integrated Buck Converter for Digital SoC Domains in 65nm CMOS.

, , , , , and . VLSI Circuits, page 1-2. IEEE, (2020)

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Madan Sathe

Nita Sathe-Meis

Richard Satherley

Saket Sathe

S Danischewski

 

Other publications of authors with the same name

Energy-Efficient GHz-Class Charge-Recovery Logic., , and . IEEE J. Solid State Circuits, 42 (1): 38-47 (2007)A GHz-class charge recovery logic., , and . ISLPED, page 91-94. ACM, (2005)A 1.1ghz charge-recovery logic., , and . ISSCC, page 1540-1549. IEEE, (2006)Boost Logic: A High Speed Energy Recovery Circuit Family., , and . ISVLSI, page 22-27. IEEE Computer Society, (2005)Energy efficient SoC design., and . CICC, page 1. IEEE, (2013)A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains., , , , , , , and . IEEE J. Solid State Circuits, 54 (4): 1173-1184 (2019)Resonant-Clock Latch-Based Design., , and . IEEE J. Solid State Circuits, 43 (4): 864-873 (2008)A charge-recovery 600MHz FIR filter with 1.5-cycle latency overhead., , , and . ESSCIRC, page 160-163. IEEE, (2009)An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage Regulator for Variation Tolerance in a Sub-Threshold ARM Cortex M0 Processor., , , , , , , and . VLSI Circuits, page 65-66. IEEE, (2018)A synchronous interface for SoCs with multiple clock domains., , , , and . SoCC, page 173-174. IEEE, (2004)