( en | de | ru )

 

Disambiguation of "Pamula, Rajesh"

Author of the publication

copydeleteadd this publication to your clipboard
Model Predictive Control of an Integrated Buck Converter for Digital SoC Domains in 65nm CMOS.

, , , , , and . VLSI Circuits, page 1-2. IEEE, (2020)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Danuta Pamula

Rajesh Saiju

Hybrid Power System Modelling - Simulation and Energy Management Unit Development. Uni Kassel, (2008)

Rajesh Chitta

Rajesh Saiju

Rajesh Narasimha

 

Other publications of authors with the same name

A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains., , , , , , , and . IEEE J. Solid State Circuits, 54 (4): 1173-1184 (2019)An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage Regulator for Variation Tolerance in a Sub-Threshold ARM Cortex M0 Processor., , , , , , , and . VLSI Circuits, page 65-66. IEEE, (2018)An All-Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction at 3.2-to-86 MB/S, 2.58 PJ/Bit in 65-NM CMOS., , , , , and . VLSI Circuits, page 1-2. IEEE, (2018)Computationally Enabled Minimum Total Energy Tracking for a Performance Regulated Sub-Threshold Microprocessor in 65-nm CMOS., , and . IEEE J. Solid State Circuits, 55 (2): 494-504 (2020)Computationally Enabled Total Energy Minimization Under Performance Requirements for a Voltage-Regulated 0.38-to-0.58V Microprocessor in 65nm CMOS., , , , and . ISSCC, page 312-314. IEEE, (2019)A 46-channel Vector Stimulator with 50mV Worst-Case Common-Mode Artifact for Low-Latency Adaptive Closed-Loop Neuromodulation., , , , , , , , , and . CICC, page 1-2. IEEE, (2021)Model Predictive Control of an Integrated Buck Converter for Digital SoC Domains in 65nm CMOS., , , , , and . VLSI Circuits, page 1-2. IEEE, (2020)UniCaP-2: Phase-Locked Adaptive Clocking with Rapid Clock Cycle Recovery in 65nm CMOS., , , , , and . VLSI Circuits, page 1-2. IEEE, (2020)A Single-Inductor 4-Output SoC with Dynamic Droop Allocation and Adaptive Clocking for Enhanced Performance and Energy Efficiency in 65nm CMOS., , , , , and . ISSCC, page 416-418. IEEE, (2021)A 172 µW Compressively Sampled Photoplethysmographic (PPG) Readout ASIC With Heart Rate Estimation Directly From Compressively Sampled Data., , , , , , , and . IEEE Trans. Biomed. Circuits Syst., 11 (3): 487-496 (2017)