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Disambiguation of "Hatayama, Kazumi"

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Accelerated Test Points Selection Method for Scan-Based BIST.

, , and . Asian Test Symposium, page 359-. IEEE Computer Society, (1997)

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Kazumi Seki

 

Other publications of authors with the same name

A Study of Capture-Safe Test Generation Flow for At-Speed Testing., , , , , , , , , and 1 other author(s). IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 93-A (7): 1309-1318 (2010)A parallel sequential test generation system DESCARTES based on real-valued logic simulation., , and . Asian Test Symposium, page 252-258. IEEE Computer Society, (1995)Test Generation for Multiple-Threshold Gate-Delay Fault Model., , , , and . Asian Test Symposium, page 244-. IEEE Computer Society, (2001)High Precision Measurement of Sub-Nano Ampere Current in ATE Environment., , , , , , , , , and 3 other author(s). ATS, page 139-140. IEEE, (2021)High-Resolution Low-Sampling-Rate Δ∑ ADC Linearity Short-Time Testing Algorithm., , , , , , , , , and 2 other author(s). ASICON, page 1-4. IEEE, (2019)Accurate and Fast Testing Technique of Operational Amplifier DC Offset Voltage in µV-Order by DC-AC Conversion., , , , , , , , , and 3 other author(s). ITC-Asia, page 1-6. IEEE, (2019)Scan based process parameter estimation through path-delay inequalities., , , , , , and . ISCAS, page 3553-3556. IEEE, (2010)Innovative practices session 9B innovative practices in Asia-1: From quality perspective., and . VTS, page 1. IEEE Computer Society, (2017)Innovative practices session 10B innovative practices in Asia-2: From cost perspective., and . VTS, page 1. IEEE Computer Society, (2017)Small Delay Fault Model for Intra-Gate Resistive Open Defects., , , , , , and . VTS, page 27-32. IEEE Computer Society, (2009)