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Disambiguation of "Nakao, Michinobu"

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Accelerated Test Points Selection Method for Scan-Based BIST.

, , and . Asian Test Symposium, page 359-. IEEE Computer Society, (1997)

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Michinobu Doi

 

Other publications of authors with the same name

Accelerated Test Points Selection Method for Scan-Based BIST., , and . Asian Test Symposium, page 359-. IEEE Computer Society, (1997)Low overhead test point insertion for scan-based BIST., , , , and . ITC, page 348-357. IEEE Computer Society, (1999)Application of High-Quality Built-In Test to Industrial Designs., , , , , and . ITC, page 1003-1012. IEEE Computer Society, (2002)Hardware Overhead Reduction for Memory BIST., , , and . ITC, page 1. IEEE Computer Society, (2008)A parallel sequential test generation system DESCARTES based on real-valued logic simulation., , and . Asian Test Symposium, page 252-258. IEEE Computer Society, (1995)Test Generation for Multiple-Threshold Gate-Delay Fault Model., , , , and . Asian Test Symposium, page 244-. IEEE Computer Society, (2001)Novel Fuse Scheme with a Short Repair Time to Maximize Good Chips per Wafer in Advanced SoCs., , , , , and . IEICE Trans. Electron., 96-C (1): 108-114 (2013)A BIST approach for very deep sub-micron (VDSM) defects., , , and . ITC, page 283-291. IEEE Computer Society, (2000)At-Speed Built-in Test for Logic Circuits with Multiple Clocks., , and . Asian Test Symposium, page 292-297. IEEE Computer Society, (2002)Enhancing Transition Fault Model for Delay Defect Diagnosis., , , , , , , , and . ATS, page 179-184. IEEE Computer Society, (2008)