( en | de | ru )

 

Disambiguation of "Kaul, Himanshu"

Author of the publication

copydeleteadd this publication to your clipboard
A 280mV 3.1pJ/code Huffman Decoder for DEFLATE Decompression Featuring Opportunistic Code Skip and 3-way Symbol Generation in 14nm Tri-gate CMOS.

, , , , , , , , , and . A-SSCC, page 263-266. IEEE, (2018)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Himanshu Raj

Himanshu Verma

Himanshu Tyagi

Himanshu Patel

Himanshu Ghildiyal

 

Other publications of authors with the same name

18Gbps, 50mW reconfigurable multi-mode SHA Hashing accelerator in 45nm CMOS., , , , , , , , , and . ESSCIRC, page 210-213. IEEE, (2010)Near-threshold voltage (NTV) design: opportunities and challenges., , , , , and . DAC, page 1153-1158. ACM, (2012)A 260mV 468GOPS/W 256b 4-way to 32-way vector shifter with permute-assisted skip in 22nm tri-gate CMOS., , , , , , and . ESSCIRC, page 177-180. IEEE, (2012)A 2.8GHz 128-entry × 152b 3-read/2-write multi-precision floating-point register file and shuffler in 32nm CMOS., , , , , , , and . VLSIC, page 118-119. IEEE, (2012)A 350mV-900mV 2.1GHz 0.011mm2 regular expression matching accelerator with aging-tolerant low-VMIN circuits in 14nm tri-gate CMOS., , , , , , , and . VLSI Circuits, page 1-2. IEEE, (2016)Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS., , , , , , , , , and 6 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)Active shielding of RLC global interconnects., , and . Timing Issues in the Specification and Synthesis of Digital Systems, page 98-104. ACM, (2002)A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS., , , , , , , , , and . IEEE J. Solid State Circuits, 52 (4): 940-949 (2017)A 2.9Tb/s 8W 64-core circuit-switched network-on-chip in 45nm CMOS., , , , and . ESSCIRC, page 182-185. IEEE, (2008)Clock net optimization using active shielding., , and . ESSCIRC, page 265-268. IEEE, (2003)