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Disambiguation of "Hsu, Steven"

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A 280mV 3.1pJ/code Huffman Decoder for DEFLATE Decompression Featuring Opportunistic Code Skip and 3-way Symbol Generation in 14nm Tri-gate CMOS.

, , , , , , , , , and . A-SSCC, page 263-266. IEEE, (2018)

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Eric Hsu

Yüanfang Hsü

Oscar Hsu

Eugene Hsu

Allen Hsu

 

Other publications of authors with the same name

A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS., , , , , , , , , and . IEEE J. Solid State Circuits, 52 (4): 940-949 (2017)2.4GHz, Double-Buffered, 4kb Standard-Cell-Based Register File with Low-Power Mixed-Frequency Clocking for Machine Learning Accelerators., , , , , , , , and . VLSI Technology and Circuits, page 22-23. IEEE, (2022)A 7Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS., , , , , , , and . VLSI Technology and Circuits, page 138-139. IEEE, (2022)A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS., , , , , , , and . ISSCC, page 182-184. IEEE, (2012)25.7 Time-Borrowing Fast Mux-D Scan Flip-Flop with On-Chip Timing/Power/VMIN Characterization Circuits in 10nm CMOS., , , , , , , , , and 4 other author(s). ISSCC, page 392-394. IEEE, (2020)A 1.9Gb/s 358mW 16-to-256 State Reconfigurable Viterbi Accelerator in 90nm CMOS., , , , and . ISSCC, page 256-600. IEEE, (2007)34.4Mbps 1.56Tbps/W DEFLATE Decompression Accelerator Featuring Block-Adaptive Huffman Decoder in 14nm Tri-Gate CMOS for IoT Platforms., , , , , , , , , and . ESSCIRC, page 90-93. IEEE, (2018)A 4900×m2 839Mbps Side-Channel Attack Resistant AES-128 in 14nm CMOS with Heterogeneous Sboxes, Linear Masked MixColumns and Dual-Rail Key Addition., , , , , , , , , and 2 other author(s). VLSI Circuits, page 234-. IEEE, (2019)A 250Mv, 0.063J/Ghash Bitcoin Mining Engine in 14nm CMOS Featuring Dual-Vcc Sha256 Datapath and 3-Phase Latch Based Clocking., , , , , , , , , and . VLSI Circuits, page 32-. IEEE, (2019)A Microwatt-Class Always-On Sensor Fusion Engine Featuring Ultra-Low-Power AOI Clocked Circuits in 14nm CMOS., , , , , , , , , and 1 other author(s). VLSI Circuits, page 50-. IEEE, (2019)