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Making predictive analog/RF alternate test strategy independent of training set size.

H. Ayari, F. Azaïs, S. Bernard, M. Comte, V. Kerzerho, O. Potin, and M. Renovell. ITC, page 1-9. IEEE Computer Society, (2012)

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Thomas Potinecke

Methode zur Systematisierung von Teilprozessen in der Produktentwicklung beim Einsatz von CAx-TechnologienT. Potinecke. Uni Stuttgart, (2009)

Werner Potinecke

Annette Pöting

Helmut Pöting

Leopold Potinus

Other publications of authors with the same name

Experimental EMFI detection on a RISC-V core using the Trace Verifier solution.A. Zgheib, O. Potin, J. Rigaud, and J. Dutertre. Microprocess. Microsystems, (2023)A CFI Verification System based on the RISC-V Instruction Trace Encoder.A. Zgheib, O. Potin, J. Rigaud, and J. Dutertre. DSD, page 456-463. IEEE, (2022)Software-Only Control-Flow Integrity Against Fault Injection Attacks.F. Bonnal, V. Dupaquis, O. Potin, and J. Dutertre. DSD, page 269-277. IEEE, (2023)Combined Fault Injection and Real-Time Side-Channel Analysis for Android Secure-Boot Bypassing.C. Fanjas, C. Gaine, D. Aboulkassimi, S. Pontié, and O. Potin. CARDIS, volume 13820 of Lecture Notes in Computer Science, page 25-44. Springer, (2022)Making predictive analog/RF alternate test strategy independent of training set size.H. Ayari, F. Azaïs, S. Bernard, M. Comte, V. Kerzerho, O. Potin, and M. Renovell. ITC, page 1-9. IEEE Computer Society, (2012)A CCFI Verification Scheme Based on the RISC-V Trace Encoder.A. Zgheib, O. Potin, J. Rigaud, and J. Dutertre. COSADE, volume 13979 of Lecture Notes in Computer Science, page 42-61. Springer, (2023)Smart selection of indirect parameters for DC-based alternate RF IC testing.H. Ayari, F. Azaïs, S. Bernard, M. Comte, M. Renovell, V. Kerzerho, O. Potin, and C. Kelma. VTS, page 19-24. IEEE Computer Society, (2012)All paths lead to Rome: Polymorphic Runtime Code Generation for Embedded Systems.D. Couroussé, T. Barry, B. Robisson, N. Belleville, P. Jaillon, O. Potin, H. Bouder, J. Lanet, and K. Heydemann. CS2@HiPEAC, page 17-18. ACM, (2018)CMOS/STT-MRAM Based Ascon LWC: a Power Efficient Hardware Implementation.N. Roussel, O. Potin, G. di Pendina, J. Dutertre, and J. Rigaud. ICECS 2022, page 1-4. IEEE, (2022)Fault Injection on Embedded Neural Networks: Impact of a Single Instruction Skip.C. Gaine, P. Moëllic, O. Potin, and J. Dutertre. DSD, page 317-324. IEEE, (2023)

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Disambiguation of "Potin, Olivier"

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Making predictive analog/RF alternate test strategy independent of training set size.

Please choose a person to relate this publication to

Thomas Potinecke

Werner Potinecke

Annette Pöting

Helmut Pöting

Leopold Potinus

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Potin, Olivier"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Making predictive analog/RF alternate test strategy independent of training set size.

Please choose a person to relate this publication to

Thomas Potinecke

Werner Potinecke

Annette Pöting

Helmut Pöting

Leopold Potinus

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Making predictive analog/RF alternate test strategy independent of training set size.