From post

A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency.

, , , и . Asian Test Symposium, стр. 306-311. IEEE Computer Society, (2005)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

 

Другие публикации лиц с тем же именем

Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses., , , и . ASP-DAC, стр. 720-725. IEEE Computer Society, (2007)An ECC-based memory architecture with online self-repair capabilities for reliability enhancement., , , , и . ETS, стр. 1-6. IEEE, (2015)Wrapper and TAM Co-Optimization for Reuse of SoC Functional Interconnects., и . DATE, стр. 1366-1369. ACM, (2008)Aging test strategy and adaptive test scheduling for SoC failure prediction., , , , , и . IOLTS, стр. 21-26. IEEE Computer Society, (2010)A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validation., , , и . ITC, стр. 1-8. IEEE Computer Society, (2012)DART: Dependable VLSI test architecture and its implementation., , , , , , , , , и . ITC, стр. 1-10. IEEE Computer Society, (2012)Power-Aware Multi-Frequency Heterogeneous SoC Test Framework Design with Floor-Ceiling Packing., , , и . ISCAS, стр. 2942-2945. IEEE, (2007)A DFT Method for Time Expansion Model at Register Transfer Level., , и . DAC, стр. 682-687. IEEE, (2007)An integrated DFT solution for power reduction in scan test applications by low power gating scan cell., , , , и . Integr., (2017)Interactive presentation: An SoC test scheduling algorithm using reconfigurable union wrappers., , и . DATE, стр. 231-236. EDA Consortium, San Jose, CA, USA, (2007)