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Disambiguation of "Sato, Yasuo"

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DART: Dependable VLSI test architecture and its implementation.

, , , , , , , , , and . ITC, page 1-10. IEEE Computer Society, (2012)

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Yasuo Kamata

Yasuo Tokunaga

Makoto Sato

Yasuo Nakayama

Nobuko Sato

 

Other publications of authors with the same name

Scan-Out Power Reduction for Logic BIST., , , and . IEICE Trans. Inf. Syst., 96-D (9): 2012-2020 (2013)On-Chip Delay Measurement for In-Field Test of FPGAs., , and . PRDC, page 130-137. IEEE, (2019)Not all Delay Tests Are the Same - SDQL Model Shows True-Time., , , , , and . ATS, page 147-152. IEEE, (2006)Good Die Prediction Modelling from Limited Test Items., , , and . ITC-Asia, page 115-120. IEEE, (2018)An evaluation of defect-oriented test: WELL-controlled low voltage test., , , , and . ITC, page 1059-1067. IEEE Computer Society, (2001)On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST., , , , , , and . Asian Test Symposium, page 19-24. IEEE Computer Society, (2013)An On-Chip Digital Environment Monitor for Field Test., , , and . ATS, page 254-257. IEEE Computer Society, (2014)A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST., , , , and . ATS, page 203-208. IEEE Computer Society, (2016)An Approach to Improve the Resolution of Defect-Based Diagnosis., , , , and . Asian Test Symposium, page 123-. IEEE Computer Society, (2001)Effective Post-BIST Fault Diagnosis for Multiple Faults., , , , , , and . DFT, page 401-109. IEEE Computer Society, (2006)