( en | de | ru )

 

Disambiguation of "Sato, Yasuo"

Author of the publication

copydeleteadd this publication to your clipboard
DART: Dependable VLSI test architecture and its implementation.

, , , , , , , , , and . ITC, page 1-10. IEEE Computer Society, (2012)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Yasuo Kamata

Yasuo Tokunaga

Makoto Sato

Yasuo Nakayama

Nobuko Sato

 

Other publications of authors with the same name

Special session: Multifaceted approaches for field reliability.. VTS, page 96. IEEE Computer Society, (2011)Path delay test compaction with process variation tolerance., , , , , and . DAC, page 845-850. ACM, (2005)An ECC-based memory architecture with online self-repair capabilities for reliability enhancement., , , , and . ETS, page 1-6. IEEE, (2015)At-Speed Built-in Test for Logic Circuits with Multiple Clocks., , and . Asian Test Symposium, page 292-297. IEEE Computer Society, (2002)A Practical Logic BIST for ASIC Designs., , , , and . Asian Test Symposium, page 457. IEEE Computer Society, (2001)Reduction of NBTI-Induced Degradation on Ring Oscillators in FPGA., , , and . PRDC, page 59-67. IEEE Computer Society, (2014)Aging test strategy and adaptive test scheduling for SoC failure prediction., , , , , and . IOLTS, page 21-26. IEEE Computer Society, (2010)DART: Dependable VLSI test architecture and its implementation., , , , , , , , , and . ITC, page 1-10. IEEE Computer Society, (2012)A BIST approach for very deep sub-micron (VDSM) defects., , , and . ITC, page 283-291. IEEE Computer Society, (2000)A Statistical Quality Model for Delay Testing., , , , and . IEICE Trans. Electron., 89-C (3): 349-355 (2006)