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Path delay test compaction with process variation tolerance., , , , , and . DAC, page 845-850. ACM, (2005)Special session: Multifaceted approaches for field reliability.. VTS, page 96. IEEE Computer Society, (2011)An ECC-based memory architecture with online self-repair capabilities for reliability enhancement., , , , and . ETS, page 1-6. IEEE, (2015)A Statistical Quality Model for Delay Testing., , , , and . IEICE Trans. Electron., 89-C (3): 349-355 (2006)DFT Timing Design Methodology for Logic BIST., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 86-A (12): 3049-3055 (2003)At-Speed Built-in Test for Logic Circuits with Multiple Clocks., , and . Asian Test Symposium, page 292-297. IEEE Computer Society, (2002)A Practical Logic BIST for ASIC Designs., , , , and . Asian Test Symposium, page 457. IEEE Computer Society, (2001)Reduction of NBTI-Induced Degradation on Ring Oscillators in FPGA., , , and . PRDC, page 59-67. IEEE Computer Society, (2014)Aging test strategy and adaptive test scheduling for SoC failure prediction., , , , , and . IOLTS, page 21-26. IEEE Computer Society, (2010)DART: Dependable VLSI test architecture and its implementation., , , , , , , , , and . ITC, page 1-10. IEEE Computer Society, (2012)