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A novel architecture for power maskable arithmetic units., , , , , и . ACM Great Lakes Symposium on VLSI, стр. 136-140. ACM, (2003)Energy-efficient data scrambling on memory-processor interfaces., , , , и . ISLPED, стр. 26-29. ACM, (2003)Low-power embedded systems.. J. Embed. Comput., 1 (3): 303-304 (2005)Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing., , , , , и . DATE, стр. 1544-1549. EDA Consortium, San Jose, CA, USA, (2007)Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating., , , , и . PATMOS, том 6951 из Lecture Notes in Computer Science, стр. 214-225. Springer, (2011)Design of a Flexible Reactivation Cell for Safe Power-Mode Transition in Power-Gated Circuits., , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (9): 1979-1993 (2009)Enhanced clustered voltage scaling for low power., , , , и . ACM Great Lakes Symposium on VLSI, стр. 18-23. ACM, (2002)Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits., , , , и . DSD, стр. 298-303. IEEE Computer Society, (2008)Optimal sleep transistor synthesis under timing and area constraints., , , , , и . ACM Great Lakes Symposium on VLSI, стр. 177-182. ACM, (2008)An aging-aware battery charge scheme for mobile devices exploiting plug-in time patterns., , , , и . ICCD, стр. 407-410. IEEE Computer Society, (2015)