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Design of the Power6 Microprocessor., , , , , , , , , and 7 other author(s). ISSCC, page 96-97. IEEE, (2007)5.1 POWER8TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth., , , , , , , , , and 10 other author(s). ISSCC, page 96-97. IEEE, (2014)IBM POWER8 circuit design and energy optimization., , , , , , , , , and 13 other author(s). IBM J. Res. Dev., (2015)The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking., , , , , , , , , and 20 other author(s). IEEE J. Solid State Circuits, 50 (1): 10-23 (2015)17.4 A 14nm 1.1Mb embedded DRAM macro with 1ns access., , , , , , , , , and 4 other author(s). ISSCC, page 1-3. IEEE, (2015)IBM z13 circuit design and methodology., , , , , , , , , and 22 other author(s). IBM J. Res. Dev., (2015)Variability analysis for sub-100 nm PD/SOI CMOS SRAM cell., , , , , and . ESSCIRC, page 211-214. IEEE, (2004)3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4., , , , , , , , , and 4 other author(s). ISSCC, page 50-51. IEEE, (2017)IBM POWER6 SRAM arrays., and . IBM J. Res. Dev., 51 (6): 747-756 (2007)A 5.2GHz microprocessor chip for the IBM zEnterprise™ system., , , , , , , , , and 17 other author(s). ISSCC, page 70-72. IEEE, (2011)