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Hiearchical Crossbar Design for ReRAM based Write Variation Inhibition on-chip learning.

Q. Zheng, Z. Wang, J. Kang, Z. Yu, Y. Cai, and J. Xu. NVMTS, page 1-3. IEEE, (2018)

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Jian Cai

Yongjie Cai

Cuifang Cai

Cai Berg

Lijun Cai

Other publications of authors with the same name

ASAP: An Efficient and Reliable Programming Algorithm for Multi-level RRAM Cell.J. Sun, Z. Wang, J. Gao, L. Shan, Q. Wang, Y. Yang, Y. Cai, and R. Huang. IRPS, page 1-4. IEEE, (2024)A 3D multi-layer CMOS-RRAM accelerator for neural network.H. Huang, L. Ni, Y. Wang, H. Yu, Z. Wang, Y. Cai, and R. Huang. 3DIC, page 1-5. IEEE, (2016)A High-Throughput and Configurable TRNG Based on Dual-Mode Memristor for Stochastic Computing.Z. Cheng, Y. Qin, Z. Wang, F. Zou, C. Wang, Y. Cai, and R. Huang. ICTA, page 108-109. IEEE, (2023)An electronic synapse based on tantalum oxide material.X. Yang, Y. Cai, Z. Zhang, M. Yu, and R. Huang. NVMTS, page 1-4. IEEE, (2015)Rotational Pattern Recognition by Spiking Correlated Neural Network Based on Dual-Gated MoS 2 Neuristor.L. Bao, Z. Wang, Z. Yu, Y. Ling, Y. Cai, and R. Huang. Adv. Intell. Syst., 2 (11): 2000102 (2020)Hiearchical Crossbar Design for ReRAM based Write Variation Inhibition on-chip learning.Q. Zheng, Z. Wang, J. Kang, Z. Yu, Y. Cai, and J. Xu. NVMTS, page 1-3. IEEE, (2018)Enhancement of HfO2 Based RRAM Performance Through Hexagonal Boron Nitride Interface Layer.Y. Chen, Z. Wang, Z. Zhang, L. Wang, Y. Fang, J. Lou, K. Liu, J. Xu, Y. Cai, and R. Huang. NVMTS, page 1-3. IEEE, (2018)Design Considerations of Multi-Level 1S1R Cell for In-Memory Computing.J. Li, Z. Wang, C. Wang, Y. Cai, and R. Huang. ICTA, page 144-145. IEEE, (2023)Facial Action Unit Detection by Exploring the Weak Relationships Between AU Labels.M. Tian, H. Zhu, Y. Wang, Y. Cai, F. Liu, P. Lin, Y. Huang, and X. Xie. CollaborateCom (2), volume 461 of Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, page 478-495. Springer, (2022)A High Accuracy Multiple-Command Speech Recognition ASIC Based on Configurable One-Dimension Convolutional Neural Network.L. Wu, Z. Wang, M. Zhao, W. Hu, Y. Cai, and R. Huang. ISCAS, page 1-4. IEEE, (2021)

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Disambiguation of "Cai, Yimao"

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Hiearchical Crossbar Design for ReRAM based Write Variation Inhibition on-chip learning.

Please choose a person to relate this publication to

Jian Cai

Yongjie Cai

Cuifang Cai

Cai Berg

Lijun Cai

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Cai, Yimao"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Hiearchical Crossbar Design for ReRAM based Write Variation Inhibition on-chip learning.

Please choose a person to relate this publication to

Jian Cai

Yongjie Cai

Cuifang Cai

Cai Berg

Lijun Cai

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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Hiearchical Crossbar Design for ReRAM based Write Variation Inhibition on-chip learning.