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Hiearchical Crossbar Design for ReRAM based Write Variation Inhibition on-chip learning.

Q. Zheng, Z. Wang, J. Kang, Z. Yu, Y. Cai, and J. Xu. NVMTS, page 1-3. IEEE, (2018)

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Zheng-Zheng Kuang

Xing Zheng

Jiarong Zheng

Zheng Ren-Rong

Shuiying Zheng

Other publications of authors with the same name

SiDA: Sparsity-Inspired Data-Aware Serving for Efficient and Scalable Large Mixture-of-Experts Models.Z. Du, S. Li, Y. Wu, X. Jiang, J. Sun, Q. Zheng, Y. Wu, A. Li, H. Li, and Y. Chen. CoRR, (2023)Accelerating Sparse Attention with a Reconfigurable Non-volatile Processing-In-Memory Architecture.Q. Zheng, S. Li, Y. Wang, Z. Li, Y. Chen, and H. Li. DAC, page 1-6. IEEE, (2023)MobiLattice: A Depth-wise DCNN Accelerator with Hybrid Digital/Analog Nonvolatile Processing-In-Memory Block.Q. Zheng, X. Li, Z. Wang, G. Sun, Y. Cai, R. Huang, Y. Chen, and H. Li. ICCAD, page 104:1-104:9. IEEE, (2020)Lattice: An ADC/DAC-less ReRAM-based Processing-In-Memory Architecture for Accelerating Deep Convolution Neural Networks.Q. Zheng, Z. Wang, Z. Feng, B. Yan, Y. Cai, R. Huang, Y. Chen, C. Yang, and H. Li. DAC, page 1-6. IEEE, (2020)Block-Wise Mixed-Precision Quantization: Enabling High Efficiency for Practical ReRAM-based DNN Accelerators.X. Wu, E. Hanson, N. Wang, Q. Zheng, X. Yang, H. Yang, S. Li, F. Cheng, P. Pande, J. Doppa and 2 other author(s). CoRR, (2023)EMS-i: An Efficient Memory System Design with Specialized Caching Mechanism for Recommendation Inference.Y. Wang, S. Li, Q. Zheng, A. Chang, H. Li, and Y. Chen. ACM Trans. Embed. Comput. Syst., 22 (5s): 100:1-100:22 (October 2023)Improving the Robustness and Efficiency of PIM-Based Architecture by SW/HW Co-Design.X. Yang, S. Li, Q. Zheng, and Y. Chen. ASP-DAC, page 618-623. ACM, (2023)Quantum algorithm and experimental demonstration for the subset sum problem.Q. Zheng, P. Zhu, S. Xue, Y. Wang, C. Wu, X. Yu, M. Yu, Y. Liu, M. Deng, J. Wu and 1 other author(s). Sci. China Inf. Sci., 65 (8): 1-14 (2022)Processing-in-Memory Technology for Machine Learning: From Basic to ASIC.B. Taylor, Q. Zheng, Z. Li, S. Li, and Y. Chen. IEEE Trans. Circuits Syst. II Express Briefs, 69 (6): 2598-2603 (2022)Hybrid Digital/Analog Memristor-based Computing Architecture for Sparse Deep Learning Acceleration.Q. Zheng, S. Li, Y. Wang, Z. Li, Y. Chen, and H. Li. ISCAS, page 1-5. IEEE, (2024)

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Disambiguation of "Zheng, Qilin"

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Hiearchical Crossbar Design for ReRAM based Write Variation Inhibition on-chip learning.

Please choose a person to relate this publication to

Zheng-Zheng Kuang

Xing Zheng

Jiarong Zheng

Zheng Ren-Rong

Shuiying Zheng

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Zheng, Qilin"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Hiearchical Crossbar Design for ReRAM based Write Variation Inhibition on-chip learning.

Please choose a person to relate this publication to

Zheng-Zheng Kuang

Xing Zheng

Jiarong Zheng

Zheng Ren-Rong

Shuiying Zheng

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
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Chicago
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Hiearchical Crossbar Design for ReRAM based Write Variation Inhibition on-chip learning.