( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
A trimless, 0.5V-1.0V wide voltage operation, high density SRAM macro utilizing dynamic cell stability monitor and multiple memory cell access.

, , , , , , , , , , , и . A-SSCC, стр. 161-164. IEEE, (2011)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Osamu Ohguchi

Osamu Omuro

Osamu Terakado

Osamu Yamada

Osamu Watanabe

 

Другие публикации лиц с тем же именем

A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit., , , , , , , , , и 1 other автор(ы). ISSCC, стр. 320-321. IEEE, (2013)Energy efficiency deterioration by variability in SRAM and circuit techniques for energy saving without voltage reduction., , , , , , , и . ICICDT, стр. 1-4. IEEE, (2012)A 47% access time reduction with a worst-case timing-generation scheme utilizing a statistical method for ultra low voltage SRAMs., , , , , , , и . VLSIC, стр. 100-101. IEEE, (2012)A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149µm2 cell in 32nm high-k metal-gate CMOS., , , , , , , , , и 1 other автор(ы). ISSCC, стр. 348-349. IEEE, (2010)A trimless, 0.5V-1.0V wide voltage operation, high density SRAM macro utilizing dynamic cell stability monitor and multiple memory cell access., , , , , , , , , и 2 other автор(ы). A-SSCC, стр. 161-164. IEEE, (2011)A Single-Power-Supply 0.7V 1GHz 45nm SRAM with An Asymmetrical Unit-×-ratio Memory Cell., , , , , , , , , и 1 other автор(ы). ISSCC, стр. 382-383. IEEE, (2008)A 0.7 V Single-Supply SRAM With 0.495 µm2 Cell in 65 nm Technology Utilizing Self-Write-Back Sense Amplifier and Cascaded Bit Line Scheme., , , , , , , , , и . IEEE J. Solid State Circuits, 44 (4): 1192-1198 (2009)DFT Techniques for Wafer-Level At-Speed Testing of High-Speed SRAMs., , , , , , , и . ITC, стр. 164-169. IEEE Computer Society, (2002)A process-variation-tolerant dual-power-supply SRAM with 0.179µm2 Cell in 40nm CMOS using level-programmable wordline driver., , , , , , , , , и 3 other автор(ы). ISSCC, стр. 458-459. IEEE, (2009)DFT techniques for memory macro with built-in ECC., , , и . MTDT, стр. 109-114. IEEE Computer Society, (2005)