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Disambiguation of "Jung, Jaehong"

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A 4GHz 0.73psrms-Integrated-Jitter PVT-Insensitive Fractional-N Sub-Sampling Ring PLL with a Jitter-Tracking DLL-Assisted DTC.

, , , , , , , and . VLSI Circuits, page 1-2. IEEE, (2020)

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Jaehong Kim

Eva Jüngel

Präklinische Studien zur Behandlung des Nierenzellkarzinoms durch den Histondeacetylase-Inhibitor Valproat und Interferon-alpha. Uni Frankfurt Main, (2009)

Yvonne Jung

Susan Jung

Matthias Jung

 

Other publications of authors with the same name

A Fully Integrated, Low-Noise, Cost-Effective Single-Crystal-Oscillator-Based Clock Management IC in 28-nm CMOS., , , , , , , , , and 6 other author(s). IEEE J. Solid State Circuits, 59 (6): 1809-1822 (June 2024)A 17.5-Gb/s transceiver with a MaxEye-based autonomous adaptation., , , , , , and . ISCAS, page 1-4. IEEE, (2017)A 4GHz 0.73psrms-Integrated-Jitter PVT-Insensitive Fractional-N Sub-Sampling Ring PLL with a Jitter-Tracking DLL-Assisted DTC., , , , , , , and . VLSI Circuits, page 1-2. IEEE, (2020)A 52MHz -158.2dBc/Hz PN @ 100kHz Digitally Controlled Crystal Oscillator Utilizing a Capacitive-Load-Dependent Dynamic Feedback Resistor in 28nm CMOS., , , , , , , , , and 1 other author(s). ISSCC, page 60-62. IEEE, (2022)A Single-Crystal-Oscillator-Based Clock-Management IC with 18× Start-Up Time Reduction and 0.68ppm/ºC Duty-Cycled Machine-Learning-Based RCO Calibration., , , , , , , , , and 6 other author(s). ISSCC, page 58-60. IEEE, (2022)An RF Transceiver with Full Digital Interface Supporting 5G New Radio FR1 with 3.84Gbps DL/1.92Gbps UL and Dual-Band GNSS in 14nm FinFET CMOS., , , , , , , , , and 10 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)A 9.4MHz-to-2.4GHz Jitter-Power Reconfigurable Fractional-N Ring PLL for Multi-Standard Applications in 7nm FinFET CMOS Technology., , , , and . A-SSCC, page 87-90. IEEE, (2019)An All-Zero Block Detection Scheme for Low-Complexity HEVC Encoders., , and . IEEE Trans. Multim., 18 (7): 1257-1268 (2016)A Wide Frequency Range, Small Area and Low Supply Memory Interface PLL Using a Process and Temperature Variation Aware Current Reference in 3 nm Gate-All Around CMOS., , , , , , , and . A-SSCC, page 1-3. IEEE, (2023)A 2.4-to-4.2GHz 440.2fsrms-Integrated-Jitter 4.3mW Ring-Oscillator-Based PLL Using a Switched-Capacitor-Bias-Based Sampling PD in 4nm FinFET CMOS., , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)