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A Varactor-Based All-Digital Multi-Phase PLL with Random-Sampling Spur Suppression Techniques.

C. Chang, K. Lo, H. Ibrahim, M. Su, Y. Chu, and S. Jou. IEICE Trans. Electron., 99-C (4): 481-490 (2016)

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Nabil Al-Jou Jou

Shyh-Yuong Lee

Ren-Jye Shiue

Shyi-Ming Jou

Yuan-jeh Jou

Other publications of authors with the same name

Low switching noise and load-adaptive output buffer design techniques.S. Jou, S. Kuo, J. Chiu, and T. Lin. IEEE J. Solid State Circuits, 36 (8): 1239-1249 (2001)A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control.H. Yang, S. Yang, M. Hsia, Y. Lin, Y. Lin, C. Chen, C. Chang, G. Lin, Y. Chen, C. Chuang and 9 other author(s). SoCC, page 197-200. IEEE, (2011)A 12.5 Gbps CMOS input sampler for serial link receiver front end.S. Jou, C. Lin, and Y. Wang. ISCAS (2), page 1055-1058. IEEE, (2005)An ultra-low voltage hearing aid chip using variable-latency design technique.K. Chang, S. Luo, C. Huang, C. Liu, Y. Chu, and S. Jou. ISCAS, page 2543-2546. IEEE, (2014)4/2 PAM serial link transmitter with tunable pre-emphasis.C. Lin, C. Tsai, C. Chen, and S. Jou. ISCAS (1), page 952-958. IEEE, (2004)An embedded DSP core for wireless communication.S. Jou, H. Lee, Y. Chen, M. Tan, and Y. Tsao. ISCAS (4), page 524-527. IEEE, (2002)Power and area reduction in multi-stage addition using operand segmentation.C. Chan, W. Liu, C. Yang, and S. Jou. VLSI-DAT, page 1-4. IEEE, (2013)A low-power charge sharing hierarchical bitline and voltage-latched sense amplifier for SRAM macro in 28 nm CMOS technology.C. Hong, Y. Chiu, J. Zhao, S. Jou, W. Wang, and R. Lee. SoCC, page 160-164. IEEE, (2014)Full-digital high throughput design of adaptive decision feedback equalizers using coefficient-lookahead.W. He, Y. Lin, J. Hung, and S. Jou. ASICON, page 1-4. IEEE, (2015)A 10-Gb/s, 1.24 pJ/bit, Burst-Mode Clock and Data Recovery With Jitter Suppression.M. Su, W. Chen, P. Wu, Y. Chen, C. Lee, and S. Jou. IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (3): 743-751 (2015)

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Disambiguation of "Jou, Shyh-Jye"

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A Varactor-Based All-Digital Multi-Phase PLL with Random-Sampling Spur Suppression Techniques.

Please choose a person to relate this publication to

Nabil Al-Jou Jou

Shyh-Yuong Lee

Ren-Jye Shiue

Shyi-Ming Jou

Yuan-jeh Jou

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Jou, Shyh-Jye"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Varactor-Based All-Digital Multi-Phase PLL with Random-Sampling Spur Suppression Techniques.

Please choose a person to relate this publication to

Nabil Al-Jou Jou

Shyh-Yuong Lee

Ren-Jye Shiue

Shyi-Ming Jou

Yuan-jeh Jou

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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A Varactor-Based All-Digital Multi-Phase PLL with Random-Sampling Spur Suppression Techniques.